1. 1-1 SYS Module System Clocks FXTAL BCLK Reset Circuit Reset Conditions Bootstrap Initialization

2. 1-2 The NET+ARM Clocks There are 4 clock symbols referred to by documentation –F CRYSTAL – External Crystal Frequency (between xtal1 & xtal2) Or Oscillator Connected to xtal1 pin –F SYSCLK – Central Clock; ARM core clock –F XTAL – Timing Reference for subsystems –BCLK – System Bus Clock; I/O, Memory Development Board / BSP Clock Configuration –F CRYSTAL – 18.432 MHz –F SYSCLK – 44.2368 MHz –BCLK – 44.2368 MHz –F XTAL – 3.6864 MHz

3. 1-3 F SYSCLK Generation F SYSCLK is determined by F CRYSTAL, PLLTST* & PLLCNT –PLLTST* is pin on NET+ARM chip When Hi, F SYSCLK determined by PLLCNT and F CRYSTAL When Lo, F SYSCLK is simply = F CRYSTAL –PLLCNT is a field in the PLL control register with range 0..15 If PLLCNT <= 3, Else, PLLTST* = 3.3V (Crystal Input)

4. 1-4 F XTAL Generation F XTAL is determined by F CRYSTAL, or PLLCNT & External Oscillator, and PLLTST* PLLTST* = 3.3V (Crystal) PLLTST* = 0V (Ext. Oscillator) If PLLCNT <= 3, Else, So, range of F XTAL is 1/18(F XTAL1) to 1/6(F XTAL1)

5. 1-5 BCLK The System Bus Clock, BCLK is controlled by the two bit configuration field, BSPEED, in the System Control Register, as a fraction of F SYSCLK : –00 – ¼ Speed –01 – ½ Speed –10 – Full Speed –11 – Reserved Note: The reset condition is ’00’

6. 1-6 Reset Circuit - Five sources: Power-up, External, Watchdog, ENI, SW Power-up Reset (special ground pad produces active high reset pulse when power voltage is outside specifications) - CPU, EFE, DMA, ENI, GEN, MEM, SER External Reset (drive RESET* pin active low during power-up) - CPU, EFE, DMA, ENI, GEN, MEM, SER Watchdog Reset (watchdog timer configured for system reset) - CPU, EFE, DMA, ENI, GEN, MEM, SER

7. 1-7 SYS Module ENI Reset - CPU, EFE, DMA, GEN, SER Software Reset - EFE, DMA, GEN, SER

8. 1-8 SYS Module The following GEN Module register fields are not affected by ENI or Software Reset: - BSPEED, BCLKD (general control register) - PortA, PortB, PortC

9. 1-9 Hardware reset requirements From the Hardware Reference Guide Vcc becomes stable (3.0 – 3.6 Volts) Reset pin is de-asserted 40 msec later Or reset line is pulsed for 1 usec while running Recommend using reset part on board

10. 1-10 Reset Circuit - Five sources: Power-up, External, Watchdog, ENI, SW Power-up Reset (special ground pad produces active high reset pulse when power voltage is outside specifications) - CPU, EFE, DMA, ENI, GEN, MEM, SER External Reset (drive RESET* pin active low during power-up) - CPU, EFE, DMA, ENI, GEN, MEM, SER Watchdog Reset (watchdog timer configured for system reset) - CPU, EFE, DMA, ENI, GEN, MEM, SER

11. 1-11 After reset is de-asserted 512 clocks after reset goes away, NET+ARM starts fetching instructions from CS0, location 0x0 During this time, the entire memory map is CS0 Execution from FLASH only Program Execution begins

12. 1-12 The Hardware RESET State Each module of the NET+ARM is reset All internal registers set to zero except… –Values specifically set with bootstrap resistors –CS0 special register considerations Maximum wait states (0xF = 15) CS0 is the only valid chip select (V bit is SET) Port size copied from bootstrap settings System Clock runs at quarter speed

13. 1-13 The ARM Vector table AddressVector 0x0000 0000RESET 0x0000 0004Undefined Instruction 0x0000 0008SWI Software Interrupt 0x0000 000CAbort (Prefetch) Bus Error Inst Fetch 0x0000 0010Abort (Data) Bus Error Data Fetch 0x0000 0014Reserved (not used) 0x0000 0018IRQ Interrupt 0x0000 001CFIRQ Interrupt

14. 1-14 SYS Module Bootstrap Initialization - During power-up reset, the system bus address bits are used to configure internal NET+50 chip functionality - NET+50 provides internal pull-up resistors on all address lines. External pull-down resistors can be used to configure the address control bits to set the internal register bits to a zero state

15. 1-15 SYS Module Bootstrap Initialization ADDR[27] Endian configuration 0 Little-endian 1 Big-endian Note: Inverted endian bit is loaded into LENDIAN (bit 31) of System Control Register ADDR[26] CPU Bootstrap 0 CPU disabled (GEN_BUSER set to 1) 1 CPU enabled (GEN_BUSER set to 0)

16. 1-16 SYS Module Bootstrap Initialization ADDR[25] Bus Arbitration (GEN_IARB) 0 Use External system bus arbiter 1 Use Internal system bus arbiter ADDR[24:23] CS0 Bootstrap “00” Bootstrap disabled “01” 32-bit SRAM port; 15 wait states “10” 32-bit DRAM port; 15 wait states “11” 16-bit SRAM port; 15 wait states

17. 1-17 SYS Module Bootstrap Initialization ADDR[22:20] ENI Configuration ( sets ENIMODE bits of General Control Register) “000” GPIO mode “001” 1284 mode “010” Reserved “011” Reserved “100” 16-bit Shared Ram mode “101” 8-bit Shared Ram mode “110” 16-bit FIFO mode, w/ 8K Shared Ram “111” 8-bit FIFO mode, w/8K Shared Ram

18. 1-18 SYS Module Bootstrap Initialization ADDR[19:09] GEN_ID Setting ( sets GEN_ID bits of System Status Register) user-defined for application-specific configuration ADDR[08] Reserved ADDR[07] ENI Control PSIO* (ENI Control Register) 0 PSIO* 1 Normal Note: Inverted address bit is loaded into PSIO (bit 9) of ENI Control Register

19. 1-19 SYS Module Bootstrap Initialization ADDR[06] ENI Control WR_OC 0 Output Driver is TTL 1 Output Driver is “Open Collector” ADDR[05] ENI Control DINT2* 0 INT2* pin configured for pulsed interrupt from ENI 1 PINT1* or PINT2* selectable by ENI ADDR[04] ENI Control I_OC 0 Output Driver is TTL 1 Output Driver is “Open Collector”

20. 1-20 SYS Module Bootstrap Initialization ADDR[03] ENI Control DMAE* 0 Enable DACK*, DRQO*, DRQ1* for FIFO mode 1 Disable FIFO mode DMA ADDR[02] Reserved ADDR[01] ENI Control EPACK* 0 ACK pin is configured as active low Data Acknowledgement signal 1 ACK pin is configured as active low WAIT signal ADDR[00] ENI Control PULINT* 0 Interrupts are issued via pulsed interrupt register 1 Interrupts are issued via STSINT or VDAINT bits