1. 1 CSE370, Lecture 14 Lecture 14 u Logistics n Midterm 1: Average 90/100. Well done! n Midterm solutions online n HW5 due date delayed until this Friday u Last lecture n Finished combinational logic n Introduction to sequential logic and systems u Today n Memory storage elements íLatches íFlip-flops n State Diagrams

2. 2 CSE370, Lecture 14 Example from last time u Door combination lock n Enter three numbers in sequence and the door opens n As each number is entered, press ‘new’ n If there is an error the lock must be reset n After the door opens the lock must be reset n Inputs: Sequence of numbers, reset, new n Outputs: Door open/close n Memory: Must remember the combination n Memory: Must remember which state we are in

3. 3 CSE370, Lecture 14 The “WHY” slide u Memory storage elements n In order to do fun problems like the door combination lock, we must know the building blocks (like how you had to learn AND and OR before you could do functional things). Be patient --- once you know these elements, you can build a lot of meaningful functions u State diagrams n For combinational logic, truth table was an invaluable visualization tool for a function. For sequential logic, state diagram serves as a way to visualize a function.

4. 4 CSE370, Lecture 14 How do we store info? Feedback u Two inverters can hold a bit n As long as power is applied u Storing a new memory n Temporarily break the feedback path "0" "1" "stored bit" "remember" "load" "data" "stored bit"

5. 5 CSE370, Lecture 14 The SR latch u Cross-coupled NOR gates n Can set (S=1, R=0) or reset (R=1, S=0) the output RQ Q S Reset Set SRQ 00hold 010 101 11disallow

6. 6 CSE370, Lecture 14 SR latch behavior u Truth table and timing Reset Hold Set Reset Race R S Q Q' 100 R S Q Q' SRQ 00hold 010 101 11disallow NOR output is 1 Only when both inputs are 0

7. 7 CSE370, Lecture 14 SR latch is glitch sensitive u Static 0 hazards can set/reset latch n Glitch on S input sets latch n Glitch on R input resets latch R S Q Q' 0 0

8. 8 CSE370, Lecture 14 State diagrams u How do we characterize logic circuits? n Combinational circuits: Truth tables n Sequential circuits: State diagrams u First draw the states n States  Unique circuit configurations u Second draw the transitions between states n Transitions  Changes in state caused by inputs

9. 9 CSE370, Lecture 14 Example: SR latch u Begin by drawing the states n States  Unique circuit configurations n Possible values for feedback (Q, Q') R S Q Q' possible oscillation between states 00 and 11 (when SR=00) Q Q' 0 1 Q Q' 1 0 Q Q' 0 0 Q Q' 1 1 SR=00 SR=11 SR=00 SR=10 SR=01 SR=00 SR=10 SR=00 SR=01 SR=11 SR=10 SR=01 SR=10 SR=11 SRQ 00hold 010 101 11disallow

10. 10 CSE370, Lecture 14 Observed SR latch behavior u The 1–1 state is transitory n Either R or S “gets ahead” n Latch settles to 0–1 or 1–0 state ambiguously n Race condition  non-deterministic transition íDisallow (R,S) = (1,1) R S Q Q' SR=00 SR=10 Q Q' 0 1 Q Q' 1 0 SR=10 SR=01 SR=00 SR=01

11. 11 CSE370, Lecture 14 The D latch: store it and look it up u Output depends on clock n Clock high: Input passes to output n Clock low: Latch holds its output u Latches are level sensitive and “transparent” DQ Q CLK Input Output CLK D Q latch

12. 12 CSE370, Lecture 14 The D flip-flop u Input sampled at clock edge n Rising edge: Input passes to output n Otherwise: Flip-flop holds its output u Flip-flops can be rising-edge triggered or falling-edge triggered DQ Q CLK Input Output CLK D Q ff

13. 13 CSE370, Lecture 14 The D flip-flop DQ Q CLK Input Output CLK D Q ff

14. 14 CSE370, Lecture 14 The D latch DQ Q CLK Input Output CLK D Q latch

15. 15 CSE370, Lecture 14 How do we make a D flip flop? u Edge triggering is difficult n You can do this at home: íLabel the internal nodes íDraw a timing diagram íStart with Clk=1 Q D Clk W Y X Z Q’

16. 16 CSE370, Lecture 14 How do we make a D flip flop? Q D Clk W Y X Z Q’ When Clk  0 then Y (set for SR-latch block ) becomes Z’=D and X (reset for SR-latch block) becomes W’=D’ so Q becomes D This is stable until D or the Clk switches If Clk=1 then X=Y=0 and SR-latch block holds previous values of Q,Q’ also Z=D’ and W=Z’=D While Clk=0, if D switches then Z becomes 0 and X and W hold their previous values and Y=X’=D as before. Falling edge-triggered flip-flop

17. 17 CSE370, Lecture 14 Terminology & notation DQ Q CLK Input Output Falling-edge triggered D flip-flop DQ Q CLK Input Output Rising-edge triggered D flip-flop DQ Q CLK Input Output Negative D latch DQ Q CLK Input Output Positive D latch

18. 18 CSE370, Lecture 14 behavior is the same unless input changes while the clock is high CLK D Q ff Q latch Latches versus flip-flops DQ Q CLK DQ Q

19. 19 CSE370, Lecture 14 The master-slave D DQ CLK Input Master D latch DQ Output Slave D latch X

20. 20 CSE370, Lecture 14 T flip-flop u Full name: Toggle flip-flop u Output toggles when input is asserted n If T=1, then Q  Q' when CLK  n If T=0, then Q  Q when CLK  CLK Q TQ > Input(t) Q(t) Q(t +  t) 000 011 101 110 Input

21. 21 CSE370, Lecture 14 Clear and preset in flip-flops u Clear and Preset set flip-flop to a known state n Used at startup, reset u Clear or Reset to a logic 0 n Synchronous: Q=0 when next clock edge arrives n Asynchronous: Q=0 when reset is asserted íDoesn't wait for clock íQuick but dangerous u Preset or Set the state to logic 1 n Synchronous: Q=1 when next clock edge arrives n Asynchronous: Q=1 when reset is asserted íDoesn't wait for clock íQuick but dangerous