1. Chapter 12 Digital Logic Circuit Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.

2. Context  12.1 Analog and Digital Signals  12.2 The Binary Number System  12.3 Boolean Algebra  12.4 Karnaugh Maps and Logic Design  12.5 Combinational Logic Modules  12.6 Sequential Logic Modules

3. Analog and Digital Signals An analog signal is an electric signal whose value varies in analogy with a physical quantity (e.g., temperature, force, or acceleration). Voltage analog of internal combustion engine in-cylinder pressure

4. A digital signal can take only a finite number of values. Digital representation of an analog signal

5. The most common digital signals are binary signals. Take only one of two discrete values and is therefore characterized by transitions between two states. A binary signal

7. The Binary Number System  Binary numbers are based on powers of 2, whereas the decimal system is based on powers of 10. For example, the number 372 in the decimal system can be expressed as:  while the binary number 10110 corresponds to the following combination of powers of 2: 10110 = (1 x 24) + (0 x 23) + (1 x 22) + (1 x 21) + (0 x 20) 372 = (3 x 102) + (7 x 101) + (2 x 100)

8.  The rightmost bit is called the least significant bit, or LSB, and the leftmost bit is called the most significant bit, or MSB. Four bits are usually termed a nibble, 8 bits is called a byte, and 16 bits (or 2 bytes) is a word.

9. CHECK YOUR UNDERSTANDING

10. Addition and Subtraction Examples of binary addition Examples of binary subtraction

11. Conversion from decimal to binary

12. CHECK YOUR UNDERSTANDING

13. Complement and Negative Number  One convention, called the sign-magnitude convention makes use of a sign bit, usually positioned at the beginning of the number, for which a value of 1 represents a minus sign and a value of 0 represents a plus sign.  An 8-bit binary number would consist of 1 sign bit followed by 7 magnitude bits.

14. (a) An 8-bit sign-magnitude binary number; (b) an 8-bit ones complement binary number; (c) an 8-bit twos complement binary number

15.  A sign bit is also used to indicate whether the number is positive (sign bit = 0) or negative (sign bit = 1). However, the magnitude of the binary number is represented by the true magnitude if the number is positive and by its ones complement if the number is negative.

16. CHECK YOUR UNDERSTANDING EXAMPLE 12.1 Twos Complement Operation

17. CHECK YOUR UNDERSTANDING

18.  In the hexadecimal (or hex) code, the bits in a binary number are subdivided into groups of 4. Since there are 16 possible combinations for a 4-bit number, the natural digits in the decimal system (0 through 9) are insufficient to represent a hex digit. To solve this problem, the first six letters of the alphabet are used. For example, 1010 0111 2 = A7 16 0010 1001 2 = 29 16 The Hexadecimal System

19. CHECK YOUR UNDERSTANDING EXAMPLE 12.2 Conversion from Binary to Hexadecimal Problem

20. CHECK YOUR UNDERSTANDING

21. Boolean Algebra Logical addition and the OR gate Logical multiplication and the AND gate

22. Example of logic function implementation with logic gates

23. Solution of a logic problem using logic gates

24. Complements and the NOT gate

25. De Morgan’s Theorems  Any logic function can be implemented by using only OR and NOT gates, or only AND and NOT gates.

26. Rule of Boolean algebra

27. Proof of rule 16 by perfect induction

28. De Morgan’s laws

29. Sum-of-products and product-of-sums logic functions

30. CHECK YOUR UNDERSTANDING EXAMPLE 12.3 Simplification of Logical Expression Problem

31. CHECK YOUR UNDERSTANDING EXAMPLE 12.4 Realizing Logic Functions from Truth Tables Problem

32. CHECK YOUR UNDERSTANDING

33. CHECK YOUR UNDERSTANDING EXAMPLE 12.5

34. Equivalence of NAND and NOR gates with AND and OR gates

35. CHECK YOUR UNDERSTANDING EXAMPLE 12.6

36. CHECK YOUR UNDERSTANDING EXAMPLE 12.7

37. CHECK YOUR UNDERSTANDING EXAMPLE 12.8

38. CHECK YOUR UNDERSTANDING

39. The XOR (Exclusive OR) Gate XOR gate Realization of an XOR gate

40. CHECK YOUR UNDERSTANDING

41. CHECK YOUR UNDERSTANDING EXAMPLE 12.9

42. CHECK YOUR UNDERSTANDING EXAMPLE 12.10 Logic circuit realization of a full adder

44. There is a procedure that utilizes a map describing all possible combinations of the variables present in the logic function of interest. This map is called a Karnaugh map, after its inventor. The row and column assignments for two or more variables are arranged so that all adjacent terms change by only 1 bit. Each map consists of 2 N cells, where N is the number of logic variables. Karnaugh Maps and Logic Design

45. Each cell in a Karnaugh map contains a miniterm, that is, a product of the N variables that appear in our logic expression. Two-, three-, and four- variable Karnaugh maps

46. Truth table and Karnaugh map representations of a logic function Karnaugh map for a four-variable expression

47. Karnaugh map for the function W’˙X˙Y’˙Z+ W‘˙X’˙Y’˙Z + W˙X’˙Y’˙Z’ + W˙X˙Y’˙Z

48. SUM-OF-PRODUCTS REALIZATIONS  Begin with isolated cells. These must be used as they are, since no simplification is possible.  Find all cells that are adjacent to only one other cell, forming two-cell subcubes.  Find cells that form four-cell subcubes, eight-cell subcubes, and so forth.  The minimal expression is formed by the collection of the smallest number of maximal subcubes.

49. CHECK YOUR UNDERSTANDING EXAMPLE 1211

50. CHECK YOUR UNDERSTANDING

51. CHECK YOUR UNDERSTANDING EXAMPLE 12.12

52. CHECK YOUR UNDERSTANDING

53. CHECK YOUR UNDERSTANDING EXAMPLE 12.13

54. CHECK YOUR UNDERSTANDING EXAMPLE 12.14

55. CHECK YOUR UNDERSTANDING EXAMPLE 12.15

56. PRODUCT-OF-SUMS REALIZATIONS  Solve for the 0s exactly as for the 1s in sum-of- products expressions.  Complement the resulting expression.

57. CHECK YOUR UNDERSTANDING EXAMPLE 12.16

58. CHECK YOUR UNDERSTANDING

59. CHECK YOUR UNDERSTANDING EXAMPLE 12.17

60. CHECK YOUR UNDERSTANDING

61. CHECK YOUR UNDERSTANDING EXAMPLE 12.18

62. CHECK YOUR UNDERSTANDING

63. CHECK YOUR UNDERSTANDING EXAMPLE 12.19

64. CHECK YOUR UNDERSTANDING

65. 4-to-1 MUX Multiplexers Internal structure of the 4-to-1 MUX

66. Functional diagram of four-input MUX

67. CHECK YOUR UNDERSTANDING

68. Read-Only Memory (ROM) Read-only memory A 2-to-4 decoder

69. CHECK YOUR UNDERSTANDING

70. Internal organization of SRAM

71.  A flip-flop is a bistable device; that is, it can remain in one of two stable states (0 and 1) until appropriate conditions cause it to change state. Thus, a flip-flop can serve as a memory element.  A flip-flop has two outputs, one of which is the complement of the other. Latches and Filp-Flop

72. RS Flip-Flop  When R = S = 0, the flip-flop remains in its present state (whether 1 or 0).  When S = 1 and R = 0, the flip-flop is set to the 1 state (thus, S, for set).  When S = 0 and R = 1, the flip-flop is reset to the 0 state (thus, R, for reset).  It is not permitted for both S and R to be equal to 1. (This would correspond to requiring the flip-flop to set and reset at the same time.)

73. Timing diagram for the RS flip-flop

74. Logic gate implementation of the RS flip- flop

75. CHECK YOUR UNDERSTANDING EXAMPLE 12.21

76. CHECK YOUR UNDERSTANDING

77. The D flip-flop: (a) functional diagram; (b) symbol; (c) timing waveforms; and (d) IC schematic

78. On the basis of the rules stated in this section, the state of the D flip-flop can be described by the following truth table: where the symbol ↑ indicates the occurrence of a positive transition.

79. JK Flip-Flop  When J and K are both low, no change occurs in the state of the flip-flop.  When J = 0 and K = 1, the flip-flop is reset to 0

80. The JK flip-flop: (a) functional diagram; (b) device symbol; and (c) IC schematic

81. Truth table for the JK flip-flop  When J = 1 and K = 0, the flip-flop is set to 1. When both J and K are high, the flip-flop will toggle between states at every negative transition of the clock input, denoted from here on by the symbol ↓.

82. CHECK YOUR UNDERSTANDING

83. CHECK YOUR UNDERSTANDING EXAMPLE 12.22

84. CHECK YOUR UNDERSTANDING EXAMPLE 12.23

85. Digital Counters  A counter is a sequential logic device that can take one of N possible states, stepping through these states in a sequential fashion. When the counter has reached its last state, it resets to 0 and is ready to start counting again.

86. Binary up counter functional representation, state table, and timing waveforms

87. Decade counter: (a) counting sequence; (b) functional diagram; and (c) IC schematic

88. Divide-by-8 circuit

90. CHECK YOUR UNDERSTANDING EXAMPLE 12.24 Divider Circuit Problem

91. Divider circuit timing diagram

92. Three-bit synchronous counter

93. CHECK YOUR UNDERSTANDING EXAMPLE 12.25 Ring Counter

94. A 4-bit parallel register

95. A 4-bit shift register

96. Homework Problem