1. 1 Flip Flops, Registers Today: Latches, Flip FlipsFirst Hour: Types of Latches, Flip Flips –Section 6.1.4-6.1.6 of Katz’s Textbook –In-class Activity #1 Second Hour: Storage and Shift Registers Section 7.1 of Katz’s Textbook –In-class Activity #2

2. 2 State Diagrams for Latches State Behavior of R-S Latch Truth Table Summary of R-S Latch Behavior

3. 3 State Diagram: R-S Latch Theoretical R-S Latch State Diagram

4. 4 Observed R-S Behavior Very difficult to observe R-S Latch in the 1-1 state Ambiguously returns to state 0-1 or 1-0 A so-called "race condition"

5. 5 Making Other Latches J K Q Q + HOLD 0 0 0 0HOLD 0 0 1 1 RESET 0 1 0 0RESET 0 1 1 0 SET 1 0 0 1SET 1 0 1 1 TOGGLE 1 1 0 1TOGGLE 1 1 1 0 NEXT STATE TABLE Simplify by coupling inputs i.e., one input determines the other

6. 6 D Latch J K Q Q + HOLD 0 0 0 0HOLD 0 0 1 1 RESET 0 1 0 0RESET 0 1 1 0 SET 1 0 0 1SET 1 0 1 1 TOGGLE 1 1 0 1TOGGLE 1 1 1 0 NEXT STATE TABLE D Q Q + RESET 0 0 0RESET 0 1 0 SET 1 0 1SET 1 1 1 Let J = D, K = D D Also called D flip-flop if edge-triggered

7. 7 T Latch J K Q Q + HOLD 0 0 0 0HOLD 0 0 1 1 RESET 0 1 0 0RESET 0 1 1 0 SET 1 0 0 1SET 1 0 1 1 TOGGLE 1 1 0 1TOGGLE 1 1 1 0 NEXT STATE TABLE Let J = T, K = T T Q Q + HOLD 0 0 0HOLD 0 1 1 TOGGLE 1 0 1TOGGLE 1 1 0 NEXT STATE TABLE T Also called T flip-flop if edge-triggered

8. 8 R-S Clocked Latch: used as storage element in narrow width clocked systems its use is not recommended! however, fundamental building block of other flipflop types J-K Flipflop: versatile building block can be used to implement D and T FFs usually requires least amount of logic to implement ƒ(In,Q,Q+) but has two inputs with increased wiring complexity because of 1's catching, never use master/slave J-K FFs edge-triggered varieties exist D Flipflop: minimizes wires, much preferred in VLSI technologies simplest design technique best choice for storage registers T Flipflops: don't really exist, constructed from J-K FFs usually best choice for implementing counters Preset and Clear inputs highly desirable!! Comparison of FFs

9. 9 Timing issues revisited Timing issues revisited Set Reset Toggle Problem: Keeps toggling! R S Q Q Latch Q Q J K

10. 10 Master section - clock high J-K inputs generate P outputs Master section - clock high J-K inputs generate P outputs Slave section - clock low Ps are unchanging and generate Qs Slave section - clock low Ps are unchanging and generate Qs J-K Master/Slave F-F Two-stage memory element Two-stage memory element Two-phase clock operation - Feedback has no effect until next time clock is high

11. 11 Timing: master-slave Master Stage Slave Stage Sample inputs while clock high Sample inputs while clock low Uses time to break feedback path from outputs to inputs! Correct Toggle Operation

12. 12 Edge-triggered FFs 1's Catching problem: - a 0-1-0 glitch on the J or K inputs leads to a state change! - I.e. If input 1 any time during the clock period, it will be interpreted as a 1 for computing output => forces designer to use hazard-free logic Solution: edge-triggered logic called “Flip-flops” Negative Edge-Triggered D flipflop Schematic when clock is high: R=S=0 I.e. Hold state

13. 13 Step-by-Step Analysis Edge-triggered Flipflops Negative edge-triggered D FF when clock goes high-to-low new data (D) is latched Negative edge-triggered D FF when clock remains low data is held

14. 14 Latches vs Flip-Flops Input/Output Behavior of Latches and Flipflops Type When Inputs are Sampled When Outputs are Valid unclocked always propagation delay from latch input change level clock high propagation delay from sensitive (Tsu, Th around input change latch falling clock edge) positive edge clock lo-to-hi transition propagation delay from flipflop (Tsu, Th around rising edge of clock rising clock edge) negative edge clock hi-to-lo transition propagation delay from flipflop (Tsu, Th around falling edge of clock falling clock edge) master/slave clock hi-to-lo transition propagation delay from flipflop (Tsu, Th around falling edge of clock falling clock edge)

15. 15 TTL schematics 7474 7476 Bubble here for negative edge triggered device Timing Diagram: Behavior the same unless input changes while the clock is high Edge triggered device sample inputs on the event edge Transparent latches sample inputs as long as the clock is asserted

16. 16 Do Activity #1 Now Q Q D Clk R S D’ D D D D Holds D when clock goes low Holds D when clock goes low Edge-triggered D-flipflop J K Q Q + HOLD 0 0 0 0HOLD 0 0 1 1 RESET 0 1 0 0RESET 0 1 1 0 SET 1 0 0 1SET 1 0 1 1 TOGGLE 1 1 0 1TOGGLE 1 1 1 0 J-K NEXT STATE TABLE

17. 17 Sequential Logic Components Flipflops:Flipflops: most primitive "packaged" sequential circuits More complex sequential building blocks: –Storage registers, Shift registers, Counters – Available as components in the TTL Catalog –Registers »Store a word (4 to 64 bits) »E.g.: Pentium has several registers –Counters »Count thru a sequence of states »E.g., the seconds display on a clock. –Both of these have many variations.

18. 18 Storage Registers Storage registersStorage registers store data, without changing it. –A D F/F is a 1-bit storage register. A Register FileA Register File stores a group of words of data. –You specify which word to read or write. Random-Access MemoryA Random-Access Memory is like a large register file. It may store 32MB of data or more.

19. 19 Multibit Storage Registers Clocks in 4 bits in parallel, or resets to 0. use D F/Fs in groups to make a multibit register

20. 20 74171 Quadruple D F/F with Clear This stores 4 bits in parallel No bubble indicates positive edge triggered The /CLR clears all 4 bits Triangle indicates clock input

21. 21 Register Variants Sometimes there’s also a LOAD input. –When LOAD is false, the F/F doesn’t change. –When LOAD is true during the clock edge, the F/F updates itself. Sometimes the outputs are 3-state or open collector. –This allows several registers to be connected to the same output wire

22. 22 74377 Octal D F/Fs with Enable Stores an 8 bit number Positive edge triggered... but only when /EN is active LO

23. 23 74374 Octal D F/Fs with 3-State Outputs Stores an 8 bit number Positive edge triggered /OE is active LO output enable Determines when register contents are visible at the outputs /OE is active LO output enable Determines when register contents are visible at the outputs Note: LW uses different labels from the 377, and from Katz!

24. 24 Register Files You read or write one word at a time. 74670 4-by-4 Register File with 3-State Outputs 4 words of 4 bits each Data in: D1,D2,D3,D4Data out: Q1,Q2,Q3,Q4 Read selects: RB,RAWrite selects: WB,WA Active low Active low read enable /GR, write enable /GW Can read and write simultaneously. No clock. Read or write when enables asserted. Watch out for glitches! To write Word 1, set GW = 0 and (WB, WA) to (0,1) To read Word 2, set GR = 0 and (RB, RA) to (1,0) To write Word 1, set GW = 0 and (WB, WA) to (0,1) To read Word 2, set GR = 0 and (RB, RA) to (1,0) Store several words

25. 25 Random Access Memories Same idea as a register file, but optimized for very many words. Small RAM: 256 4-bit words. Larger RAM: 4 million 8-bit words. More details later.

26. 26 Shift Registers Some registers are designed to change their stored data. Shift registers shift their bits left or right. For example, right shift: Original contents1000 Shift right:0100 Shift again:0010 …and again:0001 … once more, wrapping:1000 Application: send a word to a modem bit-by-bit. We need some way to initialize the shift register.

27. 27 Input and Output Serial inputSerial input The shift register doesn’t wrap around from right to left. Instead, the user provides the new leftmost bit. Parallel inputParallel input You can specify the whole word at once. Serial outputSerial output The bit just shifted off the right is visible at a pin. Parallel outputParallel output Every stored bit is visible at an output pin. This uses more pins, which can be a problem.

28. 28 74194 -more- 4 bit bidirectional universal shift register 4 modes set by S1,S0 00:hold data (QA,QB,QC,QD) 01:shift right (SR,QA,QB,QC) 10:shift left (QB,QC,QD,SL) 11:parallel load 4 modes set by S1,S0 00:hold data (QA,QB,QC,QD) 01:shift right (SR,QA,QB,QC) 10:shift left (QB,QC,QD,SL) 11:parallel load Positive edge triggered SL (aka LSI): left shift input SR (aka RSI): right shift input SL (aka LSI): left shift input SR (aka RSI): right shift input /CLR: asynchronous clear

29. 29 74194 continued Notation conflicts: –LogicWorks uses SL, SR. Katz uses LSI, RSI. –LW uses A,B,C,D for inputs and QA,QB,QC,QD for outputs. –Motorola uses P0,P1,P2,P3 for inputs, Q0,Q1,Q2,Q3 for outputs and D SR & D SL for serial inputs. NoteNote that the normal LW convention is that A is the lo-order bit. This is the way you normally connect the hex keyboard and the hex display. For the 194, A and QA are the hi-order bits. It's confusing. Right shift in more detail. All together on the rising clock: SR  QA, QA  QB, QB  QC, QC  QD, QD is lost. Connecting QD to SR makes a circular shift register. Left shift in more detail. SL  QD, QD  QC, QC  QB, QB  QA, QA is lost.

30. 30 Do Activity #2 Now Due: End of Class Today RETAIN THE LAST PAGE (#3)!! For Next Class: Bring Randy Katz Textbook, & TTL Data Book Required Reading: – Sec 7.2, 7.3 of Katz This reading is necessary for getting points in the Studio Activity!