1. Face-Recognition In Intelligent Sureillence System Feng Zhao zhaofeng@ic.sjtu.edu.cn 2007 Nov.

2. Why We do Start from a industry Project –A more advanced DVR(Digital Video Record) –Want to integrate FR in one chip Face Recognition –High compute load –Have to Implement in PC(Cognitec “FaceVACS® ”) –Have designed a Embedded FR System on DSP –Face Recognition in a FPGA

3. What We have Done Embedded Solution –17fps for CIF PowerPC405 Hardware accelerator State Machine (Fully Hardware Logic) –200fps for CIF (Freq:100M)

4. Prototype Board Xilinx XUP Virtex-II Pro Development System (Used in “Embedded System Design” Course) Processor: PPC 405 Processor clock frequency: 300.000000 MHz Bus clock frequency: 100.000000 MHz BRAM Memory : about 200KBytes

5. Technology Roadmap Embedded Solution(Done 2007.07) –Powerpc405+coreConnect –Integrate Video Port to PLB Bus –XUP V2Pro Prototype Full Hardware Solution(Done 2007.09) –State Machine based –Xtream DSP –XUP V2Pro Prototype Commercial Product(2007.11) –Based on full hardware Solution –Spartan-DSP(SA1800) –For IS’VISION Corp.(Largest FR Solution Provider) –Substitute IS’VISION’s TI DSP based solutions Multi-Channel Product(CY08) –4-Channel –D1

6. Solution Evaluation Start from OpenCV (Intel PC) Porting to ucLinux (Embedded SW) MicroBlaze(FSL) + HA (SW/HW) PowerPC(PLB/OPB) + HA (SW/HW) State Machine + XtremeDSP –System C level modeling –C Modeling and profiling –VerilogHDL Coding

7. Performance

8. Evaluation Conclution Embedded Solution –17fps for CIF PowerPC405 Hardware accelerator State Machine (Fully Hardware Logic) –200fps for CIF (Freq:100M)

9. Hardware arch for algorithm

10. Original PC Embedded

11. What Continue to do Demo on V5 Open Source