1. 1 COSC 3P92 Cosc 3P92 Week 8 Lecture slides It is dangerous to be right when the government is wrong. Voltaire (1694 - 1778)

2. 2 COSC 3P92 RISC machines Reduced instruction set computer vs. CISC -- complex... (680x0, IBM 360,...) CISC technology has evolved highly complex instruction sets, to bridge "semantic gap" between hardware and software –simplify compilers –alleviate software crisis –improve architecture quality But has CISC design gone "over the top"? If one looks at the software being executed, it is typically simple and unsophisticated, and do not exploit the sophisticated features of CISC instruction sets.

3. 3 COSC 3P92 Software studies (all values represent %)

4. 4 COSC 3P92 RISC philosophy: create an instruction set that lets you do the most common computations, while maximising their efficiency To do this, throw away microprogramming, and aim for instructions which execute in 1 cycle RISC chips have many features which are exportable to contemporary CISC chips; also, there are points of contention about design. There are also chips which seem to have both CISC and RISC-like qualities.

5. 5 COSC 3P92 History IBM 801RISC1MIPS Year198019821983 No. of instructions1203955 Control memory size (Kbit)000 Instr. size (bits)323232 Machine typeregisterregisterregister IBM 370/168 VAX-11/780 Dorado iAPX-432 Year1973197819781982 No. of instructions208303270222 Control memory size (Kbit)42048013664 Instr. size (bits)16-4816-4568-246-321 Machine typeregisterregisterstackstack

6. 6 COSC 3P92 History The IBM 801 project (1975) was designed with the following principles: –choose an instruction set to be a good target for a compiler –provide a hardware engine that can execute its instructions in one machine cycle –design the storage hierarchy so that the control engine does not have to wait for storage access –base the entire system design on an optimizing compiler

7. 7 COSC 3P92 RISC vs CISC: characteristics RISCCISC 1. simple instns taking 1 cycle 1. complex instns taking multiple cycles 2. only LOADs, STOREs 2. any instn. may access memory access memory 3. designed around pipeline3. designed around instn. set 4. instns. executed by h/w4. instns interpreted by microprogram 5. Fixed format instns5. variable format instns 6. Few instns and modes6. Many instns and modes 7. Complexity in the compiler 7. Complexity in the microprogram 8. Multiple register sets8. Single register set

8. 8 COSC 3P92 RISC Design * Sacrifice everything to reduce the data path cycle time. * Microcode is not magic. Five steps: 1.Find key operations in intended applications. 2. Design optimal data path for these operations. 3. Design instructions which perform these operations on this data path. 4. Add new instructions if they don't slow down machine 5. Repeat for other resources (cache, MMU,...)

9. 9 COSC 3P92 Design Issues Single-cycle instructions –key RISC characteristic –rapid execution of simple instructions –complex instns will require more compiled code Only LOAD and STORE instns access memory –permits pipelining efficiency –not as many addressing modes

10. 10 COSC 3P92 Design Issues Maximal pipelining –permits n instructions in n cycles Problems: (i) memory accesses take 2 cycles (ii) jumps ruin pipeline Solutions: For (i): - hardware interlock (wait) - use incorrect register (means that compiler needs to correct situation)

11. 11 COSC 3P92 Design Issues –For (ii): need to optimise pipeline (instruction order) at compile time. No Micro-code –eliminate interpretation, max. data path efficiency. –frees ALOT of chip space Fixed format instructions –simple to decode OPCODE C DEST SOURCE OFFSET 1 0 = Do not set condition codes 1 = Set condition codes 0 = Not immediate 1 = Immediate Bits 7 1 5 5 1 13 Fig. 8-7. RISC 1 basic instruction format.

12. 12 COSC 3P92 Reduced instruction set –because of simple instruction format –with RISC I, offset can double as operand, yielding 3 operand instructions. –to effect complex addressing, need to generate code to explicitly construct the addressing More compile-time complexity –compiler technology is the reason that RISC technology is feasible. –compiled code is executed directly, so compiler must account for delayed instructions, register usage,... –lack of sophisticated instructions adds compiler complexity (eg. Multiply) Multiple register sets – RISC chips have lots of registers (100's!) – techniques for organizing them.

13. 13 COSC 3P92 Register Usage Need to maximize pipeline, minimise memory access. memory traffic in CISC is largely caused during procedure calling RISC organises registers to minimize (remove) memory accesses during procedure calls –overlapping register window organisation Fig. 8.8 The 32 registers visible to a program at any instant of time.

14. 14 COSC 3P92 CWP - current window pointer Output and input register sets double up in usage during procedure calls No stack needed UNLESS –too many parameters –parameters are too large in value –too many nested calls cause all registers to be used... in which case standard stack techniques are used. Remember: most programs are simple! Philosophical point: – Registers vs Memory ?

15. 15 COSC 3P92 RISC vs CISC Benchmarking computers is difficult –effects of hardware organisation (I/O, memory mgmt,...) –different chip technologies: ECL (emitter coupled logic) vs MOS –operating system –language effects: C vs Prolog vs COBOL vs... –type of program: recursive vs iterative Overlapping register windows: –not part of MIPS chip –could it be exported to CISC chips too?

16. 16 COSC 3P92 CISC vs RISC Compiler writing for RISC Delayed JUMP 100LOADX, A 101ADD1, A 102JUMP105 103ADDA, B 104SUBC, B 105STOREA, Z 106 Normal Branch 100LOADX, A 101ADD1, A 102JUMP106 103NO-OP 104ADDA, B 105SUBC, B 106STOREA, Z Delayed Branch Optimized Delayed Branch 100LOADX, A 101JUMP105 102ADD1, A 103ADDA, B 104SUBC, B 105STOREA, Z 106

17. 17 COSC 3P92 Compilers need to account for: –memory delays –jump delays –register allocation –simple instruction set RISC compilers need to make the best use of registers –preferable to use all the regs in a single window (and not memory) Optimising compilers can do data flow analysis on programs to see when variables are "active"

18. 18 COSC 3P92 Example 1: Pentium II (CISC) Recall: –instruction formats [5.13] –addressing modes [5.26] Instruction set: [5.33] CISC instruction set –design determined for back-compatability –superscalar microprocessor tries to “deconstruct” CISC instns into pipelineable microinstructions –erratic variants for instn type, register usage, addressing modes –[reference pages]

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22. 22 COSC 3P92 Example 2: UltraSparc II Recall: formats [5.14] –addressing: either immediate or register –only load, store access memory [5.34]

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26. 26 COSC 3P92 Example 4: MIPS R4000 Microprocessor without Interlocking Pipe Stages similarities with UltraSPARC: –64 bit design –LOAD/STORE architecture –2^64 byte-addressable memory –paging, coprocessors,... differences: –configurable to either Big- or Little-endian (byte ordering in words) –no register file or register windows –no condition codes: results of tests saved in regs –8 stage pipeline Generally, MIPS does not give as orthogonal an instruction set to programmer as SPARC, for hardware efficiency sake.

27. 27 COSC 3P92 No window file: –pro: »with saved space, can fit MMU, cache controller, MUL/DIV on chip »removes overhead of saving 500 regs when multitasking »registers not fixed in purpose –con: »more (software) overhead in procedure calling

28. 28 COSC 3P92 Summary Pentium II: –2-address, 32-bit CISC –irregular UltraSPARC –3-address, 64-bit RISC –128-bit bus –somewhat complex formats MIPS –another 64-bit RISC SPARC vs. MIPS orthogonal instns optimised H/W register windows none software MUL/DIV hardware MUL/DIV condition codes none

29. 29 COSC 3P92 Itanium P4 has severe problems (IA-32) –CISC –2 Address Memory Oriented ISA –Small Register Set »6 registers –Lack of Regs requires internal renaming of Regs, »requires out of order execution to compensate for memory reference waits »Hence expensive h/w –Deep pipeline (result of out of order execution), »Flushing becomes very expensive –Speculative execution causing traps to set. A large portion of the P4 is devoted to dealing with the problems of its CISC architecture.

30. 30 COSC 3P92 Itanium. Itanium (EPIC a better RISC) –Has many functional units each able to work in parellel. –3 Address Risc. –Much of the instruction work (reordering etc.) is moved to the compiler. –Parallelism of the h/w is known by the compiler »Take advantage of the h/w producing efficient code. –Simple Memory Model 2 64 bytes –128 registers – reducing memory references »32 static »96 for a register stack (like register windows of Ultra Sparc III. –Procedure calls put the call stack on the register stack »Parameters a placed in registers as part of the call frame. »Local variable are allocated on the stack by the procedure.

31. 31 COSC 3P92 Itanium.. –128 Floating point registers –64 Predicate registers »Used for conditional branch prediction. –8 branch registers –128 special-purpose »Inter application communication.

32. 32 COSC 3P92 Itanium… Branch Prediction Branches are removed by allowing all instructions to execute. –A Condition sets a predicate bit –An instruction will write back the result if the predicate is true. (a) An if statement. (b) Generic assembly code for a). (c) A conditional instruction.

33. 33 COSC 3P92 Itanium…. CMOVZ, will execute if R1 is 0 CMOVN, will execute if R1 is not 0 This means: –Executing a few instr. Is cheaper then a branch. –Most branches can be eliminated. »No pipeline problems.

34. 34 COSC 3P92 Itanium….. Predicate registers are pairs, –E.g. P4 is false then P5 is true. And visa versa. –Any instruction can be predicated.

35. 35 COSC 3P92 The end