1. ECE 353 Introduction to Microprocessor Systems Michael G. Morrow, P.E. Week 2

2. Learning Styles Assessment Only an assessment of preference 11-97-53-35-79-11 ACT-81262REF SEN310132-INT VIS1197-1VRB SEQ24193-GLO

3. Topics Microprocessor Organization Organization of Microprocessor Systems Endian-ness ARM History and Characteristics ARM7TDMI Implementation ADuC7026 Overview

4. Microprocessor Components Register file Program counter General purpose registers Hidden registers

5. Microprocessor Components ALU Buses

6. Microprocessor Components Memory interface Signal conventions  Active  Active-low  Active-high  Asserted  Negated Control and timing unit

7. A Simple  P Architecture A less simple architecture

8. Instruction Set Architectures (ISA) Complex Instruction Set (CISC) Single instructions for complex tasks (string search, block move, FFT, etc.) Usually have variable length instructions Registers often have specialized functions

9. Instruction Set Architecture (ISA) Reduced Instruction Set (RISC) Instructions for simple operations only Usually fixed length instructions Large orthogonal register sets Many processors are hybrids

10. Register Architectures Accumulator One instruction operand comes from a dedicated register (the accumulator) closely coupled to the ALU Register-Memory Instruction operands can be obtained from both registers and memory Commonly used in CISC machines Load-Store All operands must be in general-purpose registers Only a very limited number of instructions (loads/stores) can “touch” memory Commonly used in RISC machines

11. Microprocessor System Organization Memory Architectures Von Neumann architecture Harvard architecture Input/Output (I/O)  Memory-mapped I/O  Isolated I/O Examples

12. Microprocessor System Organization Programmer’s Model aka Register View Memory Maps

13. Endian-ness Byte Ordering for Little Endian vs. Big Endian Memory Address+0+1+2+3 Big Endian Byte 0 Byte 1 Byte 2 Byte 3 MSB in the lowest (first) memory address Little Endian Byte 3 Byte 2 Byte 1 Byte 0 LSB in the lowest (first) memory address Byte 0 Byte 1 Byte 2 Byte 3 Most Significant Byte (MSB) Least Significant Byte (LSB)

14. 14 ARM Ltd  Founded in November 1990  Spun out of Acorn Computers  Designs the ARM range of RISC processor cores  Licenses ARM core designs to semiconductor partners who fabricate and sell to their customers.  ARM does not fabricate silicon itself  Also develop technologies to assist with the design- in of the ARM architecture  Software tools, boards, debug hardware, application software, bus architectures, peripherals etc

15. 15 ARM Partnership Model

16. 16 ARM Powered Products

17. ARM Characteristics Designed to be a simple, efficient RISC core Small die area Low power Low interrupt latency These characteristics enabled ARM to become dominant in the cell phone market. Most cell phones contain a heterogenous multiprocessor SoC with an ARM and a DSP Advanced ARM designs (Cortex Mx, Ax) have become much more sophisticated (i.e. Intel Xscale in PDAs), but histoically had less success in penetrating other markets where power consumption issues are not as severe

18. ARM7TDMI Implementation The ARM7TDMI uses the ARM v4T ISA All instructions are conditional The ARM7TDMI is a basic load-store RISC Sixteen GP registers (R15-R0) with banking Three stage pipeline (FDE) No caches Support for ARM (32-bit) and Thumb (16-bit) instruction sets Multiply-accumulate (MAC) unit (Rd  Ra*Rb+Rc) On-chip hardware debug support

19. ARM7TDMI Processor Block Diagram

20. ARM7TDMI Processor Core

21. Analog Devices ADuC7026 ARM7TDMI core 62kB flash (16-bit), 8kB SRAM (32-bit) In-circuit programmable, JTAG debug 41.78MHz PLL with programmable divider Little-endian Numerous digital peripherals GPIO Timers (GP x4 including watchdog/wake-up) UART/I 2 C/SPI serial interfaces 3-phase PWM External memory interface (16-bit multiplexed) Analog input/output 12 in, 4 out Voltage reference and temperature sensor

22. ADuC7026 Block Diagram

23. ADuC7026 Memory Map

24. ADuC7026 Pin-Out (LQFP-80)

25. Assessment Team ConcepTest In-Class Address Decoding Exercise

26. Wrapping Up Week 3 reading is chapters 3 & 6 from the textbook, the ARM7TDMI Technical Reference Manual chapter 2, and Supplement #1 (Learn  Content) Pre-Quiz #2 to be done by Monday 2/6 class Homework #1 due Wednesday 2/8

27. Team ConcepTest A 32-bit word with value 0x54AF8 is stored in memory at address 0x00008DC44 in a little-endian system. Show the address and contents of each byte of memory used. What type of operation is described by (PC)  (PC) – 0x0C? A 20-bit address space has a 32KB RAM at base address 38000h, and a 128KB ROM at B0000h. Draw and label the memory map.

28. In-Class Exercise Design decode logic for the following devices with the indicated control inputs: 64Kx8 ROM (/CS, /OE) at 0x04XXXX 1Mx8 RAM (/CS, /OE, /WE) at 0xA00000 Input Port (/OE) at 0xFXXX00 Output Port (/WR) at 0x1XXXXX In all cases, assume a 24-bit address bus (A23:0) and active low control signals (/RD, /WR)

29. TMS320C671X Organization

30. Register View of a Simple  P aka “Von Neumann” or “Princeton” architecture

31. Register View of a Simple  P with Isolated I/O space Most microprocessors do NOT have isolated I/O. The Intel x86 microprocessors do.

32. Register View of a Simple  P with Separate Code and Data Memories aka “Harvard” architecture