1. Basic Adders and Counters Implementation of Adders in FPGAs ECE 645: Lecture 3

2. Required Reading Chapter 5, Basic Addition and Counting, Sections 5.1-5.5, pp. 75-85. Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design

3. Required Reading Chapter 9, Using Carry and Arithmetic Logic Spartan-3 Generation FPGA User Guide http://www.xilinx.com/support/documentation/spartan-3_user_guides.htm

4. Half-adder x y c s HA x + y = ( c s ) 2 2 1 xyc s 00110011 01010101 00010001 01100110

5. Half-adder Alternative implementations (1) s = xy + xy b) a) s = x  y c = xy c = x + y

6. c) c = xy s = xc + yc = xc  yc Half-adder Alternative implementations (2)

7. Full-adder x y c out s FA x + y + c in = ( c out s ) 2 2 1 xy c out s 0000111100001111 0011001100110011 0001011100010111 0110100101101001 c in 0101010101010101

8. Full-adder Alternative implementations (1) a) s = (x  y)  c in c out = xy + c in (x  y) s c c

9. Full-adder Alternative implementations (2) s = x  y  c in = xyc in + xyc in + xyc in + xyc in c out = xy + xc in + yc in b)

10. Full-adder Alternative implementations (3) c) xyc out s 00110011 01010101 0101 c in

11. x y A2 A1 XOR D 01 C in C out S p g Full-adder Alternative implementations (4) Implementation used to generate fast carry logic in Xilinx FPGAs xyc out 00110011 01010101 yyyy c in p = x  y g = y s= p  c in = x  y  c in

15. Latency of a k-bit ripple-carry adder T ripple-add = T FA (x,y  c out ) + + (k-2)  T FA (c in  c out ) + + T FA (c in  s) Latency  k  T FA Latency  k

18. Overflow for signed numbers (1) Indication of overflow Positive + Positive = Negative Negative + Negative = Positive Formulas Overflow 2’s complement = x k-1 y k-1 s k-1 + x k-1 y k-1 s k-1 = = c k  c k-1

19. Overflow for signed numbers (2) x k-1 y k-1 c k-1 c k s k-1 overflow c k  c k-1 0000111100001111 0011001100110011 0101010101010101 0001011100010111 0110100101101001 0100001001000010 0100001001000010

20. Implementation of Adders in FPGAs

21. TechnologyLow-costHigh- performance 120/150 nmVirtex 2, 2 Pro 90 nmSpartan 3Virtex 4 65 nmVirtex 5 45 nmSpartan 6 40 nmVirtex 6 Xilinx FPGA Devices

22. Altera FPGA Devices TechnologyLow-costMid-rangeHigh- performanc e 130 nmCycloneStratix 90 nmCyclone IIStratix II 65 nmCyclone IIIArria IStratix III 40 nmCyclone IVArria IIStratix IV

23. 23 ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) General structure of an FPGA

24. 24 ECE 448 – FPGA and ASIC Design with VHDL

25. 25 ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Xilinx Spartan 3 FPGAs

26. 26 ECE 448 – FPGA and ASIC Design with VHDL CLB Structure

27. 27 ECE 448 – FPGA and ASIC Design with VHDL CLB Slice Structure Each slice contains two sets of the following: Four-input LUT Any 4-input logic function, or 16-bit x 1 sync RAM (SLICEM only) or 16-bit shift register (SLICEM only) Carry & Control Fast arithmetic logic Multiplier logic Multiplexer logic Storage element Latch or flip-flop Set and reset True or inverted inputs Sync. or async. control

28. 28 ECE 448 – FPGA and ASIC Design with VHDL LUT (Look-Up Table) Functionality Look-Up tables are primary elements for logic implementation Each LUT can implement any function of 4 inputs

29. 29 ECE 448 – FPGA and ASIC Design with VHDL COUT D Q CK S R EC D Q CK R EC O G4 G3 G2 G1 Look-Up Table Carry & Control Logic O YB Y F4 F3 F2 F1 XB X Look-Up Table F5IN BY SR S Carry & Control Logic CIN CLK CE SLICE Carry & Control Logic

30. xy COUT 00110011 01010101 yyyy CIN Propagate = x  y Generate = y Sum= Propagate  CIN = x  y  CIN x y Carry & Control Logic in Xilinx FPGAs

31. Carry & Control Logic in Spartan 3 FPGAs LUT Hardwired (fast) logic

32. Simplified View of Spartan-3 FPGA Carry and Arithmetic Logic in One Logic Cell

33. Simplified View of Carry Logic in One Spartan 3 Slice

35. Critical Path for an Adder Implemented Using Xilinx Spartan 3 FPGAs

36. Number and Length of Carry Chains for Spartan 3 FPGAs

37. Bottom Operand Input to Carry Out Delay T OPCYF 0.9 ns for Spartan 3

38. 0.2 ns for Spartan 3 Carry Propagation Delay t BYP

39. Carry Input to Top Sum Combinational Output Delay T CINY 1.2 ns for Spartan 3

40. Critical Path Delays and Maximum Clock Frequencies (into account surrounding registers)

41. Major Differences between Xilinx Families Number of CLB slices per CLB Number of LUTs per CLB slice Look-Up Tables Number of adder stages per CLB slice Spartan 3 Virtex 4 Virtex 5, Virtex 6, Spartan 6 4-input6-input 4 2 2 2 4 4

42. Altera Cyclone III Logic Element (LE) – Normal Mode

43. Altera Cyclone III Logic Element (LE) – Arithmetic Mode

44. Altera Stratix III, Stratix IV Adaptive Logic Modules (ALM) – Normal Mode

45. Altera Stratix III, Stratix IV Adaptive Logic Modules (ALM) – Arithmetic Mode

46. Bit-Serial & Digit-Serial Adders

48. Bit-serial adder xixi yiyi sisi c0c0 start c i+1 clk

49. Digit-serial adder d d d xixi yiyi sisi c0c0 start c i+1 clk

50. Addition of a Constant

51. Addition of a constant (1) x k-1 x k-2... x 1 x 0 y k-1 y k-2... y 1 y 0 variable constant + x k-1 x k-2... x h+1 x h x h-1... x 0 y k-1 y k-2... y h+1 1 0... 0 variable constant + x h x h-1... x 0 s k-1 s k-2... s 1 s 0 s k-1 s k-2... s h+1

52. Addition of a constant (2)... HA/ MHA HA/ MHA HA/ MHA HA/ MHA x0x0 x h-1 xhxh x h+1 x h+2 x k-1 x k-2.... x0x0 x h-1 xhxh s h+1 s h+2 s k-1 s k-2... If y i = 0 Half-adder (HA) y i = 1 Modified half-adder (MHA) ckck

53. Modified half-adder x y c s MHA x + y + 1 = ( c s ) 2 2 1 xyc s 00110011 01010101 01110111 10011001

54. HA x1x1 x2x2 x k-1 x k-2.... s1s1 s2s2 s k-1 s k-2... x0x0 x0x0 ckck Incrementer MHA x1x1 x2x2 x k-1 x k-2.... s1s1 s2s2 s k-1 s k-2... x0x0 x0x0 ckck Decrementer

57. Asynchronous Adders

58. Possible solutions to the carry propagate problem 1. Detect the end of propagation rather than wait for the worst-case time 2. Speed-up propagation via look-ahead carry skip carry select, etc 3. Limit carry propagation to within a small number of bits 4. Eliminate carry propagation through the redundant number representation

60. Analysis of carry propagation Probability of carry generation = (x i y i = 11) Probability of carry propagation = (x i y i = 01 or 10) Probability of carry anihilation = (x i y i = 00 or 11) j j-1....... i+1 i 1 0 … 1 …0 … 1 1 1 1 … 0 …1 … 0 1 Probability of carry propagating from position i to position j = 11 or 00 01 or 10  probability of propagation probability of anihilation =

61. Expected length of the carry chain that starts at position i (1) Expected length(i, k) = Length of the carry chain Probability of the given length Probability of propagation till the end of adder Distance till the end of adder

62. Expected length of the carry chain that starts at position i (2) Expected length(i, k) = For i << k Expected length of the carry propagation is  2