1. Timers

2. Range of timers Watchdog timer: Included in all devices (watchdog timer+). Its main function is to protect the system against malfunctions but it can instead be used as an interval timer if this protection is not needed. Basic timer1: Present in the MSP430x4xx family only. It provides the clock for the LCD and acts as an interval timer. Real-time clock: In which the basic timer has been extended to provide a real- time clock in the most recent MSP430x4xx devices. Timer_A: Provided in all devices. It typically has three channels and is much more versatile than the simpler timers just listed. Timer_A can handle external inputs and outputs directly to measure frequency, time-stamp inputs, and drive outputs at precisely specified times, either once or periodically. Timer_B: Included in larger devices of all families. It is similar to Timer_A with some extensions that make it more suitable for driving outputs such as pulse-width modulation. It lacks a feature of sampling inputs in Timer_A that is useful in communication.

3. Watchdog Timer The main purpose of the watchdog timer is to protect the system against failure of the software, such as the program becoming trapped in an unintended, infinite loop. Left to itself, the watchdog counts up and resets the MSP430 when it reaches its limit. The code must therefore keep clearing the counter before the limit is reached to prevent a reset. The operation of the watchdog is controlled by the 16-bit register WDTCTL. It is guarded against accidental writes by requiring the password WDTPW = 0x5A in the upper byte. A reset will occur if a value with an incorrect password is written to WDTCTL. The lower byte of WDTCTL contains the bits that control the operation of the watchdog timer. The ~RST/NMI pin is also configured using this register. Most bits are reset to 0 after a power-on reset (POR) but are unaffected by a power-up clear (PUC). The lower byte of the watchdog timer control register WDTCTL

4. Watchdog Timer The watchdog counter is a 16-bit register WDTCNT, which is not visible to the user. It is clocked from either SMCLK (default) or ACLK, according to the WDTSSEL bit. The reset output can be selected from bits 6, 9, 13, or 15 of the counter. Thus the period is 2 6 = 64; 512; 8192; or 32,768 (default) times the period of the clock. This is controlled by the WDTISx bits in WDTCTL. The intervals are roughly 2, 16, 250, and 1000 ms if the watchdog runs from ACLK at 32 KHz. The watchdog is always active after the MSP430 has been reset. By default the clock is SMCLK, which is in turn derived from the DCO at about 1 MHz. The default period of the watchdog is the maximum value of 32,768 counts, which is therefore around 32 ms. You must clear, stop, or reconfigure the watchdog before this time has elapsed. If the watchdog is left running, the counter must be repeatedly cleared to prevent it counting up as far as its limit. This is done by setting the WDTCNTCL bit in WDTCTL. The bit automatically clears again after WDTCNT has been reset.

5. Watchdog Timer The MSP430 is reset if the watchdog counter reaches its limit. There are two levels of reset. The watchdog causes a power-up clear, which is the less drastic form. Most registers are reset to default values but some retain their contents, which is vital so that the source of the reset can be determined. The watchdog timer sets the WDTIFG flag in the special function register IFG1. This is cleared by a power-on reset (POR) but its value is preserved during a PUC. Thus a program can check this bit to find out whether a reset arose from the watchdog.

6. Failsafe Clock Source for Watchdog Timer+ Newer devices have the enhanced watchdog timer+ (WDT+). This includes fail-safe logic to preserve the watchdog’s clock. Suppose that the watchdog is configured to use ACLK and the program enters low-power mode 4 to wait for an external interrupt. The old watchdog (WDT) stops during LPM4 and resumes counting when the device is awakened. In contrast, WDT+ does not let the device enter LPM4 because that would disable its clock. Therefore it is not possible to use LPM4 with WDT+ active. The watchdog must first be stopped by setting WDTHOLD. Similarly, it is not possible to use LPM3 if WDT+ is active and gets its clock from SMCLK. If its clock fails, WDT+ switches from ACLK or SMCLK to MCLK and takes this from the DCO if an external crystal fails.

7. Watchdog as an Interval Timer The watchdog can be used as an interval timer if its protective function is not desired. Set the WDTTMSEL bit in WDTCTL for interval timer mode. The periods are the same as before and again WDTIFG is set when the timer reaches its limit, but no reset occurs. The counter rolls over and restarts from 0. An interrupt is requested if the WDTIE bit in the special function register IE1 is set. This interrupt is maskable and as usual takes effect only if GIE is also set. The watchdog timer has its own interrupt vector, which is fairly high in priority but not at the top. It is not the same as the reset vector, which is taken if the counter times out in watchdog mode. The WDTIFG flag is automatically cleared when the interrupt is serviced. It can be polled if interrupts are not used.

8. Basic Timer1 Basic Timer1 is present in all MSP430xF4xx devices. It provides the clock for the LCD module and generates periodic interrupts. The register BTCTL controls most of the functions of Basic Timer1 but there are also bits in the special function registers IFG2 and IE2 for interrupts. An unusual feature of this module is that BTCTL is not initialized by a reset: This must be done by the user. BTCNT1: Takes its input from ACLK and provides the clock for the LCD module at frequency fLCD. BTCNT2: Can be used independently of BTCNT1, in which case the BTSSEL bit selects the clock from ACLK or SMCLK.

9. Real-Time Clock A Real-Time Clock (RTC) module has been added to recent devices in the MSP430xFxx family. It counts seconds, minutes, hours, days, months, and years. The control register, RTCCTL, is initialized after a power-on reset, unlike BTCTL, and the RTCHOLD bit is set so that the clock does not run by default. The clock needs a 1 Hz input, which it takes from Basic Timer1. The RTC module therefore takes control over Basic Timer1 and cascades the counters as if BTDIV=1.

10. Timer_A This is the most versatile, general-purpose timer in the MSP430 and is included in all devices. There are two main parts to the hardware: Timer block: The core, based on the 16-bit register TAR. There is a choice of sources for the clock, whose frequency can be divided down (prescaled). The timer block has no output but a flag TAIFG is raised when the counter returns to 0. Capture/compare channels: In which most events occur, each of which is based on a register TACCRn. They all work in the same way with the important exception of TACCR0. Each channel can; ◦ Capture an input, which means recording the “time” (the value in TAR) at which the input changes in TACCRn; the input can be either external or internal from another peripheral or software. ◦ Compare the current value of TAR with the value stored in TACCRn and update an output when they match; the output can again be either external or internal.

11. Timer_A Request an interrupt by setting its flag TACCRn CCIFG on either of these events; this can be done even if no output signal is produced. Timer_A is modular and the number of capture/compare channels varies between devices. Most have three channels. The number of channels is sometimes appended to the name as in Timer_A3. Capture/compare channel 0 is special in two ways. Its register TACCR0 is taken over for the modulus value in Up and Up/Down modes, so that it is no longer available for its usual functions. It also has its own interrupt vector with a higher priority than the other interrupts from Timer_A, which all share a common vector. Therefore channel 0 should be chosen for the most urgent tasks if it is free.

12. Timer_A It is important to realize that all channels within Timer_A share the same timer block: There is only one TAR. This ensures that actions performed by the different channels are precisely synchronized. The drawback is that they all work at the same fundamental frequency. Outputs must be supervised by software rather than driven purely by hardware if you need them to change at different frequencies or not to be periodic at all. A few devices have two Timer_A modules, which operate with independent time bases. A general principle is to use the hardware of Timer_A for the part of an event that needs precise timing and to reserve software for the less critical parts. This means that signals to be timed should be connected directly to capture inputs so that there is no delay. Outputs should be driven directly from the timer so that they change as soon as a compare event happens. Of course this works only if suitable pins are available or there is an internal connection to the peripheral concerned. Software can then respond to the event—calculate the duration of an input or set up the next output—but the delay required for this does not compromise the timing of the signals.

13. Timer_A Simplified block diagram of Timer_A showing the timer block and capture/compare channel 1. The circles show external signals that may be brought out to pins of the device.

14. Timer Block This contains the 16-bit timer register TAR, which is central to the operation of the timer. It is controlled by the register TACTL. A timer is really no more than a counter and has no direct concept of time (the Real-Time Clock is an exception). It is the programmer’s job to establish a relation between the value in the counter and real time. This depends essentially on the frequency of the clock for the timer. It can be chosen from four sources by using the TASSELx bits: SMCLK is internal and usually fast (MegaHertz). ACLK is internal and usually slow, typically 32 KHz from a watch crystal but may be taken from the VLO in the MSP430F2xx family. TACLK is external. INCLK is also external, sometimes a separate pin but often it is connected through an inverter to the pin for TACLK so that ~INCLK = TACLK.

15. Timer Block An accurate, stable clock source is needed if the timer is to work in real time. This generally requires a crystal. An alternative is to use the frequency of the AC mains if available. This is not particularly stable over short times but power companies usually aim to keep the average frequency accurate at 50 or 60 Hz over a day. The frequency of the incoming clock can be divided down by 2, 4, or 8 if desired by configuring the IDx bits. A slower clock reduces the resolution of the timer so that events are timed less precisely. Against this, it increases the natural period of the timer before it overflows, rolls over, and restarts from 0. The period of the timer can range from 4ms with the fastest SMCLK to 16s with a 32 KHz ACLK and maximum division.

16. Timer Block These periods all apply to the Continuous mode, in which TAR cycles through its full range. The timer has four modes of operation, selected with the MCx bits: Stop (MC = 0): The timer is halted. All registers, including TAR, retain their values so that the timer can be restarted later where it left off. Up (1): The counter counts from 0 up to the value in TACCR0, the capture/compare register for channel 0. It returns to 0 on the next clock transition. The period is (TACCR0+1) counts. For example, if TACCR0 = 4, the sequence of counts is 0, 1, 2, 3, 4, 0, 1,... with period 5. Up mode is usually used when all channels provide outputs at the same frequency, often for pulse-width modulation. Continuous (2): The counter runs freely through its full range from 0x0000 to 0xFFFF, at which point it overflows and rolls over back to 0. The period is 2 16 = 65,536 counts. This mode is most convenient for capturing inputs and is also used when channels provide outputs with different frequencies or that are not periodic at all. Up/Down (3): The counter counts from 0 up to TACCR0, then down again to 0 and repeats. The period is 2×TACCR0 counts. For example, if TACCR0=3, the sequence of counts is 0, 1, 2, 3, 2, 1, 0, 1,... with period 6. This is a specialized mode, typically used for centered pulse-width modulation.

17. Timer Block Precise control of the period of the timer is available in Up and Up/Down modes. The disadvantage is the loss of channel 0, whose register TACCR0 is taken over to hold the upper limit of the count—the modulus. The count in TAR and the divider can be cleared by writing a 1 to the TACLR bit in TACTL. This also resets the direction of counting in Up/Down mode. It is a good idea to do this whenever the timer is configured to ensure that the first period will be correct. The TACLR bit automatically clears itself after use.

18. Timer Block The flag TAIFG in TACTL is set when the timer counts to 0 and a maskable interrupt is requested if the TAIE bit is set. Setting TAIFG occur only as a result of normal counting. They do not occur if the appropriate value is written directly to a register. For example, setting TACLR clears TAR but does not set TAIFG. You are strongly advised to stop the timer before modifying its operation (except the interrupt enables, interrupt flags, and TACLR) to avoid possible errors. Often the timer clock is not synchronous with the CPU clock, such as when the timer is supplied from ACLK. In this case it is best to stop the timer before reading the value of TAR. An advantage of the 16-bit architecture of the MSP430 is that registers of the timer can be read in a single instruction.

19. Capture/Compare Channels Timer_A has three channels in most MSP430s although channel 0 is lost to many applications because its register TACCR0 is needed to set the limit of counting in Up and Up/Down modes. Each channel is controlled by a register TACCTLn. The central feature of each channel is its capture/compare register TACCRn. In Capture mode this stores the “time”—the value in TAR—at which an event occurs on the input; in Compare mode it specifies the time at which the output should next be changed and an interrupt requested. The mode is selected with the CAP bit. This is cleared by default so that the channel is in Compare mode. Any mixture of capture and compare channels can be used and the mode can be switched freely from one to the other. Remember to configure pins if you want to connect them to the timer. Otherwise the timer may produce a signal but it does not appear outside the chip. Typically this needs PnSEL.x = 1 to select the module rather than digital input/output and the appropriate value in PnDIR.x for input or output.