1. S PECIAL M ANPOWER D EVELOPMENT P ROGRAMME IN VLSI – P HASE II (SMDP- II) Review For the year 2011 Resource Centres (RCs) February 10-11,2012 @ IIT Kanpur

2. S TATUS OF I NFRASTRUCTURE IIT Kharagpur NIT Rourkela Jadavpur University NIT Jamshedpur NIT Silchar Servers All are working Fine 3 (working) 3 Servers fully working 3 (working) Client machin es and networ k Working Smoothly Working absolutely fine 9 clients fully working Softwar e tools Synopsys License is not there, rest are fine All tools are used All tools except Coware and Magma working Cadence and Xilinx are in use Cadence, Mentor, Synopsys Serious problem s, if any Tool Licenses Expiry Synopsis license is over on 14th Jan

3. S TATUS OF MANPOWER GENERATED IIT Kharagpur (2010-11) NIT Rourkela (2010-11) Jadavpur University (2010-11) NIT Jamshedpur NIT Silchar Type I61102 Type II 3618 59 Type III 4247700 Type IV 12060+641200182

4. S TATUS OF FUND UTILIZATION IIT Kharagpur NIT Rourkela Jadavpur University NIT Jamshedpur NIT Silchar Date release letter received 27.10.201119.11.201121(30)/2005- VCND/HRD Dt. 04-10-10 N/INA Date UC submitted July 201129.07.2011Letter No: 058/SMDP- II/2011 Dt. 21-10-11. N/INA Balance if any 5,30,000 (Appox.) Till 31st Jan. 2012 Rs 9,01,270/- on 31st Jan, 2012. 2,21,349.00 As on 02-02- 2012 N/I3.5 lakh Problems, if any Yes** NO Balance fund awaiting. N/I ** Confirmation of continuation is required. Otherwise it would be hard to pay the salary of the project staff.

5. S TATUS OF OTHER ACTIVITIES IIT Kharagpur NIT Rourkela Jadavpur University NIT Jamshedpur NIT Silchar Participatio n in India Chip programme YesYES NoNIL IEP arranged or attended Arranged in March 2011 NO 1 AT IIT KHARAGPUR 04 Papers published YesYES 0 National Journals+3 National Conference 28 papers 03 1 International Journals+0 International Conferences Special lectures YesYESNo Invited lectures from IIT Guwahati and IIT Bombay/IIT Madras/ST Microelectronic s

6. Q UICK C HECK IIT Kharagpur NIT Rourkela Jadavpur University NIT Jamshedpur NIT Silchar Three major achieve ments So many students are doing their research or project or laboratory using the EDA tool received under SMPD Able to spread VLSI Education in and around the state thro’ Short Term course and workshop. 1. Development of 4 ICs N/I Published papers in national/international/ conferences/ refreed journals By organizing the IEP or Guest Faculty programme awareness about VLSIhas been spread Manpower production at the level of Ph. D. and Masters is continuously increasing. 2. Generation of Ph.Ds in VLSI area Students have been placed in VLSI/EDA companies/educational institutes Many IPs has been developed and some have already been fabricated. Now we are thinking of building of system level design by using those IPs. All tools are being utilized and we are ready for tape out. Able to collaborate with R & D houses for other projects. 3. Training of around 120 students of different private engineering colleges in the area of VLSI each year. Three signific ant problem s / issues Useful tools are necessary Synopsis tool License 1. Delay in tape out of chips N/I Non availability of quality lab staff Training of each tool is very much necessary Worried for discontinuation 2. Powerline UPS showed some problems

7. A DDITIONAL INFORMATION Status Website at RCFully working (www.smdp.iitkgp.ernet.in) PI visits by RC During the IEP-2011, participants prom NIT Silchar and Jadavpur University had discussed with us regarding the progress in their corresponding institutes. Jadavpur University is regularly communicating with us regarding the VLSI activities and chip design India Chip Programme coordination by RC Being done.

8. C HIPS TO S YSTEMS P ROPOSAL C ONTOUR 1. Project Name - An embedded high resolution ultrasonography system using fundamental and harmonic imaging 2.Total Outlay – 541 Lakhs (Including all institute) 3.Duration – 5 Years 4. Manpower Requirement – @ RC: 2 Research Consultant, 2 Senior Project Assistant, 1 Technician for testing, 1 Job Assistant @PI: 2 Guest Faculty per PI

9. Cadence: 5 year subscription for 20 licenses of each module indicated below Full Custom/Analog/Mixed Signal/RFIC Design Flow tool set Functional verification tool set System design and verification tool set Logic Design tool set Digital Implementation tool set Manufacturability Signoff tool set IC packaging and SiP design tool set PCB Design tool set Synopsys: 5 year subscription for 10 licenses of each module indicated below System Level Design tool set Digital and analog design & verification tool set Implementation and signoff tool set Manufacturing tool set TCAD process and device simulation tool set Mentor Graphics: 5 year subscription for tool set available under Mentor Higher Education Programme Xilinx: 5 year subscription for 50 licenses of each module indicated below Software Requirements: Xilinx Latest version with system edition Hardware Requirements: Virtex-6 and Spartan-6 boards Software Required for C2S

10. Main output from the project: i.Development of JPEG-2000 on ASIC. (IIT KGP, BESU) ii.Development of FFT/IFFT unit (IIT KGP) iii.Development of knowledge base system. (IIT KGP) iv.Telemedicine solution along with the system. (IIT KGP, BESU ) v.CAM Memory Design (JU) vi.DSP/DIP chips (NIT DGP, IIT KGP, BESU, JU) vii.Portable Low-Cost Ultrasound System design (IIT KGP, PSG College Tech.) viii.Design & Development of image and video processing algorithm (IIT KGP, PSG Coll. Tech, NIT DGP, BESU, JU) ix.Over all System Integration (IIT KGP). Application area in which system would find use: Healthcare Objective of C2S Manpower at Ph.D & Masters level proposed to be generated as a secondary outcome of the project: Same as SMDP-II Name of the PIs along with whom collaborative development work would be carried out for designing the identified targeted system: (a) IIT Kharagpur, (b) BESU, Howrah, (c) Jadavpur University, (d) NIT Durgapur, (e) PSG College of Tech. Coimbatore

11. Year wise Outputs of the C2S Work PlanMonths 0 6 12 18 24 30 36 42 48 54 60 1. Literature Survey 2. Procurement of capital equipment and Software 3. System level simulation 4. FPGA realizations for beam forming algorithms 5. Algorithm development for image compression 6. FPGA realization of image compression 7. Software development for telemedicine 8. System integration 9. Prototype design and testing