1. 11 Multi-Product Floorplan Optimization Framework for Chip Multiprocessors Marco Escalante 1, Andrew B. Kahng 2, Michael Kishinevsky 1, Umit Ogras 3 and Kambiz Samadi 4 1 Intel Corp., 2 ECE and CSE, University of California at San Diego 3 School of ECEE, Arizona State University, 4 Qualcomm Research SLIP 2015

2. 22 Outline Big Picture and Motivation Background on Tile-level Floorplanning Multi-product Chip Floorplanner – Generic Formulation – Choppability constraints for multi-product optimization Experimental results Conclusions and future work

3. 33 Big picture Interconnection networks commonly used in industry – Servers – Ring and mesh – Graphics / Throughput computing – mesh – Clients – Rings Cyclic dependency between interconnection network and floorplan – Interconnection network depends on tile and chip floorplan – Floorplan depends on interconnection network Both floorplan and interconnect topology affect Power/Performance/Area core Cache core Cache core Cache core Cache core Cache core Cache core Cache core Cache Cache should be wide enough to support link width

4. 44 Current Examples: Chip-Multiprocessors Last level cache (LLC) Memory controllers (MC) & channels I/O controller(s) QPI controller(s) Power control unit (PCU), … Core* C C C C C C C C C C C * Picture of a low core count system is drawn for illustrative purposes. “Core” box entails mid-level caches and other common blocks in all cores LLC QPIQPI PCIePCIe Memory Controller MC PCU RRR RRR RRR Same resources (building blocks) used for many SKUs Large scale distributed system!

5. 55 Multi-product FP optimization Different SKUs with varying requirements – Different number of cores, memory channels, I/O agents – …yet share the same building blocks Make the FP choppable to the optimization once and re-use for all QPI 0 QPI 1 PCIe IIO PC U QPI R3CS I QPI 2 QPI core Cache core Cache core Cache core Cache core Cache core Cache core Cache core Cache core Cache core Cache core Cache core Cache core Cache core Cache core Cache VMSE 1/2 MC VMSE 0 VMS E 3 IV Town – 15 cores Intel Xeon Server processor Haswell had 27 different SKUs, with number of cores ranging from 4 to 18

6. 66 Overview of Approach Goal: Develop an efficient and robust floorplan optimization framework for server products Involves floorplanning at two levels of hierarchy: – (1) tile-level, ~10-20 resources – (2) chip-level, many tiles (> 20 tiles) Tile-level FP considers the physical constraints due to interconnect Chip-level FP addresses choppability constraints by simultaneously optimizing the FP across product classes

7. 77 Tile Floorplanning Objective: Minimize area Subject to: – Global routing constraints – NoC link width Major resources – Core, LLC and MLC caches, Core-MLC interface, LLC/MLC - Ring interface, snoop filter, etc. – Resources can be both hard or soft – Hard blocks can rotate 90° Approach: Mixed-integer linear programming (MILP) Since tile level FP is not the focus of the paper, only major distinct properties will be mentioned Reference : S. Sutanthavibul, E. Shragowitz and J. B. Rosen, “An Analytical Approach to Floorplan Design and Optimization”, IEEE Trans. on CAD, 10(6), 1991, pp. 761-769.

8. 88 Constraints Imposed by Chip FP Routing constraint: Block i and j should not overlap in X and Y directions i j jj j Adjacency constraint: Block i and j should be adjacent j ii j i i XXX CORE XXX Router XXX

9. 99 Outline Motivation and Big Picture Background on Tile-level Floorplanner Multi-product Chip Floorplanner – Generic Formulation – Choppability constraints for multi-product optimization Experimental results Conclusions and future work

10. 10 CoreMC Core MC Core Chip Level Floorplan Overview Floorplans of each class can be easily derived through chopping operation Differences with respect to tile floorplan – Overlap constraints are met by default – Integer linear programming formulation – Simultaneous floorplan optimization across multiple product classes P1P1 x y Column 012 Row 0 Row 1 Empty Core MC Core P2P2 120 Chopped P3P3 CoreMC 120 Chopped Empty Chopped

11. 11 Preliminaries and Notations We use 1-hot binary variables u ij such that – u ij = 1 means the cell (i,j) is occupied – u ij = 0 means the cell (i,j) is empty We need to extend the definition to multiple floorplans – u s ij represents the cell (i,j) in FP “s” – Multiple types of cells, Core, Memory Controller (MC), Empty – u s ij0 means an empty cell at (i,j) in FP “s” – u s ij1 means a CORE at cell (i,j) in FP “s” – u s ij2 means an MC at cell (i,j) in FP “s” – Our formulation can consider k resource types Example at the right hand side – u 0 001 (Core), u 0 011 (Core) – u 0 101 (Core), u 0 112 (MC) ( 0,0) ( 0,1) ( 1,0) ( 1,1) FP: S 0 ( 0,0) ( 0,1) ( 1,0) ( 1,1) FP: S 1 ( 0,0) ( 0,1) ( 1,0) ( 1,1) FP: S 2 CoreMCEmpty

12. 12 Generic Problem Formulation GOAL: to find {u s ijk }’s to Minimize sum of half-perimeter of all products Constraints on number of resources – Each tile can be occupied by only one type of resource – Each product has a specified number of instances of each resource Monotonicity constraints: Suppose, product i can be chopped to j (0,0) ( 0,1) (1,0)(1,1) FP: S 0 ( 0,0) ( 0,1) ( 1,0) ( 1,1) FP: S 1 ( 0,0) ( 0,1) ( 1,0) ( 1,1) FP: S 2 Core MC Empty

13. 13 Choppability Solution = Finding {u s ijk }’s Example at right hand sice – {u 0 000, u 0 001 } = {0,1} (Core), {u 0 010, u 0 011 } = {0,1} (Core) – {u 0 100, u 0 101 } = {0,1} (Core), {u 0 110, u 0 111 } = {1,0} (MC) – {u 1 000, u 1 001 } = {0,0} (Empty), {u 1 010, u 1 011 } = {0,1} (Core) – {u 1 100, u 1 101 } = {0,0} (Empty), {u 1 110, u 1 111 } = {1,0} (MC) – {u 2 000, u 2 001 } = {0,0} (Empty), {u 2 010, u 2 011 } = {0,1} (Core) – {u 2 100, u 2 101 } = {0,0} (Empty), {u 2 110, u 2 111 } = {0,0} (Empty) ( 0,0) ( 0,1) ( 1,0) ( 1,1) FP: S 0 ( 0,0) ( 0,1) ( 1,0) ( 1,1) FP: S 1 ( 0,0) ( 0,1) ( 1,0) ( 1,1) FP: S 2 CoreMCEmpty Chop the box = Cores are converted to empty Chopping a cell means Core or MC converted to Empty

14. 14 Core/MC Count Constraints Assume – N s Core = Number of cores in FP “s” – N s MC = Number of MCs in FP “s” Example: N 0 Core = 3, N 1 Core = 1, N 2 Core = 1, N 0 HA = 1, … ( 0,0) ( 0,1) ( 1,0) ( 1,1) FP: S 0 ( 0,0) ( 0,1) ( 1,0) ( 1,1) FP: S 1 ( 0,0) ( 0,1) ( 1,0) ( 1,1) FP: S 2 CoreMCEmpty u s ij2 = 1 only if there is an MC in the cell u s ij1 = 1 only if there is an Core in the cell

15. 15 Height and Width Computations To express area, we need a way of representing height and width, but we will have “s” heights and widths For each product class i ( 0,0) ( 0,1) ( 1,0) ( 1,1) FP: S 0 ( 0,0) ( 0,1) ( 1,0) ( 1,1) FP: S 1 ( 0,0) ( 0,1) ( 1,0) ( 1,1) FP: S 2 CoreMCEmpty Shows that row r is used Shows that column c is used

16. 16 Additional Placement Constraints Sources at the boundaries – Memory controller channels and I/O controllers Contiguous tiles Adjacency constraints MCh I/O MCh I/O MCh I/O MCh I/O MCh MC

17. 17 Power- / Performance-Driven DSE We allow the number of core and memory controllers for each product to vary in a given range given target design thermal power We add constraints on maximum number of memory controllers in a given row or column

18. 18 Outline Motivation and Big Picture Background on Tile-level floorplanning Multi-product Chip Floorplanner – Generic Formulation – Choppability constraints for multi-product optimization Experimental results Conclusions and future work

19. 19 Developed Infrastructure Read a floorplan description file Generate corresponding integer linear programming formulation that is fed into CPLEX Solutions are written into an ascii file describing final floorplans of all the product classes The final floorplan description of each product class is printed as a PDF file # × Biggest product grid size: 6 × 6 N_C_0: 26 N_H_0: 4 N_C_1: 18 N_H_1: 2 # max-k constraint on HAs MC top: 1 MC bottom: 2 MC left: 1 MC right: 1 # Tile width and height information Tile width: 2 Tile height: 1 Multi-Product FP Description File

20. 20 Chopping with Four Product Classes S 0 = 34 cores, 8 MCs  S 1 = 26 cores, 4 MCs S 2 = 18 cores, 2 MCs  S 3 = 10 cores, 2 MCs MC Core MC Core MC Core MC Core MC Empty

21. 21 Chopping with Four Product Classes S 1 = 26 cores, 4 MCs  S 2 = 18 cores, 2 MCs MC Core MC Core

22. 22 Chopping with Four Product Classes S 2 = 18 cores, 2 MCs  S 3 = 10 cores, 2 MCs MC Core

23. 23 S 1 = 36 cores, 8 MCs, 8 MChs  S 2 = 27 cores, 6 MCs, 6 MChs Results with Memory Controller Channels

24. 24 Results with Memory Controller Channels S 2 = 27 cores, 6 MCs, 6 MChs  S 3 = 18 cores, 4 MCs, 4 MChs

25. 25 Conclusions & Future works Simultaneous floorplan optimization framework for CMPs across multiple products We define the concept of a choppable floorplan – Enables us to easily derive the floorplan of smaller products from those of larger Finding choppable floorplans across multiple products to reduce re-design costs and shortens time-to-market Future challenges – Joint tile and chip level floorplanning – Reducing the white space when

26. 26 BACK-UP

27. 27 S 1 = 36 cores, 8 MCs, 8 MChs  S 2 = 27 cores, 6 MCs, 6 MChs  S 3 = 18 cores, 4 MCs, 4 MChs Results with Memory Controller Channels Test Case# Binary Variables # ConstraintsCPU Runtime (s) 15953014687 289662044744 31089721814936

28. 28 MC Different Grid Size Grid size is 6 x 6 Total number of tiles = 30 Tile height = 1, Tile width = 2 Enables exploration of different tile aspect ratios

29. 29 Power- / Performance-Driven DSE (2) We consider different width and height values for different resource types

30. 30 Tile Floorplan Examples XXX CORE Router XXX MISC Pipeline Stages Logic IDI Inter- face XXX Out. Buffer XXX Sample Core FloorplanSample FP for Router &Cache Controller

31. 31 Developed Infrastructure Read a floorplan description file Generate corresponding mixed- integer programming formulation that is fed into CPLEX Solutions are written into an ascii file describing final floorplan The final floorplan description is printed as a PDF file at the end # BEGIN FP DESCRIPTION X1 A1 minAR1 maxAR1 0 X2 A2 minAR2 maxAR2 1 X3 A3 minAR3 maxAR3 1 X4 A4 minAR4 maxAR4 0 END FP DESCRIPTION # BEGIN OVERLAP CONSTRAINTS X2 X4 3 END OVERLAP CONSTRAINTS # BEGIN ADJACENCY INFO X3 X4 END ADJACENCY INFO Floorplan Description File