1. Preliminary stuff
Prof. Paul Hasler

2. Capacitor Circuits C2 Q I
Vout(t)
GND

3. Capacitor Circuits  We get an integration…. Q I C2 = Iin C2 = - Iin
dQ(t) dt
dVout(t) dt 
= Iin
C = - Iin Q I
Vout(t)
We get an integration….
GND

4. Capacitor Circuits  We get an integration…. For constant I, we get Q
dQ(t) dt
dVout(t) dt 
= Iin
C = - Iin Q I
Vout(t)
We get an integration….
GND
For constant I, we get
Iin
Vout(t) = Vstart t C2

5. Capacitor Circuits  We get an integration…. For constant I, we get t
dQ(t) dt
dVout(t) dt 
= Iin
C = - Iin Q I
Vout(t)
We get an integration….
GND
Vout(t)
For constant I, we get
Iin
Vout(t) = Vstart t C2 t

6. Capacitor Circuits C Injection Tunneling t Vtun Vdd Vout Vref Vd
Vout(t)
Injection
Tunneling t

7. Floating-Gate Systems
Prof. Paul Hasler

8. Floating-Gate Devices
Digital Memory (EEPROMs)
Analog Memory
Floating-Gate Circuits
Floating-Gate Systems
Floating-Gate Adaptation
Information Storage
Floating-Gate Transistor
Modifying Floating-Gate Charge
All of this in a standard
CMOS process
- UV photo-injection
- Electron tunneling
- Hot-electron injection

9. Floating-Gate Circuits
Capacitor-Based Circuits
Charge Modification
Decrease Floating-Gate
charge by hot-electron
injection
Increase Floating-Gate
charge by electron
tunneling
Resistors and Inductors define
the circuit dynamics
Capacitors are the natural elements
on silicon ICs

10. Electron Tunneling (oxide voltage)-1
Increasing the applied voltage decreases the effective barrier width
The range of tunneling currents span many orders of magnitude.

11. pFET Hot-Electron Injection
The injected electrons are generated
by hole impact ionizations.
Vinj = 430mV
**Injection current is proportional to source current, and is an
exponential function of Fdc.

12. Offset elimination Huge Linear Range Small Linear Range80
Directi
on of offset
due to
hot-electron
injection onto
the fl
oating gate
devices.
Output Current (nA)
Small Linear Range
Differential
-80 -3 3
Differenti
al Input Voltage
Offset is less than 1 mV.

13. Tunable Voltage SourcesCf
SELECT UP
DOWN
VOLTMETER
Tunnel
Tunneling Circuitry
Select
Vref
Inject
Injection
Circuitry
Select
Output Voltage: (if selected)
Decreased by Tunneling
Increased by Injection

14. Arrays of Prog.Voltage Sources
EPot elements are arranged in a linear array with a shift register selecting one element at a time
Speed used: ~1V/ms
( range is 100V/ms to very very slow)

15. Translinear Element using Floating-Gate Devices
Vdd
Vdd I1 I2
Iout
GND
GND
GND

16. A Single-Ended Gm-C filter using Floating-Gate Devices
Vdd
Vdd I1 I2 C C -1
Vout
Vin C
GND
GND C

17. Programming / Selectivity in FG Array
2 conditions for injection
channel current
(Gate voltage)
Large Source to drain voltage
(high field for hot electrons)

18. Programming a Floating-gate Device
Tunneling
Remove charge from floating-gate
Less control per device
Used as “global” erase
Decrease current for a given threshold
Hot-electron injection
Add electrons to the floating-gate
Isolate devices well
Program accurately
Increase current for a given gate voltage V
tun in + I

19. Basic Programming Structure
Injection
Both:
Device isolation
Gate:
Column isolation
Source-Drain:
Row isolation

20. Programming a FG Bring chip up to program voltage
Bring drain up to match Vds(run)
Set Gate volt to read current
Read Current through device
Calculate next pulse on drain
Pulse Drain voltage
Rinse and repeat V
tun + V in A + -
Offchip

21. Basic Programming Structure
(M. Kucic, P. Smith, P. Hasler, )

22. Programming Board Interface
Tes ti ng Bo
ard
Current T o
Moni
tor Dr ai n
Block SP I T o
Gat e D A C
Regu
lat or
Additional
Lev el
User
Shifters
Circuits Se le ct io n Lo gi c

23. Programming Board, v0.1

24. Answers to Typical Questions
Is storing analog charge levels on a floating-gate reliable?
Yes, we have seen little to no movement over months
(like 0.01mV in EPots)
Isn’t floating-gate programming is slow?
We are currently programming in ms times,
should get to 1-10ms times as in EEPROM,
and the process can operate in parallel.
Does this require specialized processes?
Can be built in either Double Poly or Single Poly
(i.e. digital) processes

25. Automatic Floating-Gate Programming
(NSF ITR)
Programming Algorithm
Programming Results 1 2
START
Get in Range
Select Next Element 1
cosine
Measure Current 8
Floating-Gate Bias Current (nA)
Yes No 6
< target 4
-cosine
Compute Drain V 2
Inject Element 1 2 3 4 5 6 7
Position along the Array

26. Array Programming V M 1 2 I t u n f g d T o C i r c o C i r c u i t -+ d T o C i r c o C i r c u i t

27. Applications of Floating-Gate Circuits in Systems
Programmable Filters / Adaptive Filters
Auditory / Accoustical Signal Processing
Image Processing
ADCs, DACs, etc.

28. Single-Transistor pFET Synapses
1. Store a weight value
2. Input x stored W
3. dW/dt = correlation of the
f( input , a given error signal)
Programmable and Adaptive
Analog Processing
(NSF CAREER)

29. Fourier-Based Programmable Filters
Vin
Bandpass Filters,
Exp Spaced
(Hard in DSP)
W11
W12
W13
W14
W15
W1n
W21
W22
W23
W24
W25
W2n
Iout1
Iout2
FG tuning of bandpass filters as well as coefficients…
(M. Kucic, P. Hasler, et. al )

30. Analog Speech Front-End Blocks
Analog Cepstrum
Microphone
Digital Signal
Processing
HMM
Cepstrum VQ
VQ Classifier
Analog HMM Classifier
Outputs

31. Transform Imager Our approach allows for Bio-inspired (Retina)
computation
A programmable
architecture
High-fill factor (~50%)
pixels like
CMOS imagers.
Can build in other
neuromorphic designs
into this structure

32. Layout of Imager Cell Fill Factor ~ 50% Fabricated in 0.5mm CMOS
0.5mm mm
Photo 8mmx6mm 3.2mmx2.4mm
Array x x 512
(Size) (1.72mm2) (4.4mm2)
39l = 11.7mm
30l = 9mm

34. Adaptive Floating-Gate Circuits
Full range of floating-gate circuits abilities
Continuously programming (tunneling / injecting)
therefore, circuits at a slower timescale
Equilibrium point: Tunneling current = Injection current
Fundamental operation for adaptive systems:
Adaptive Filters, Neural Networks, Neuromorphic Models of Learning

35. AFGA Behavior C V Output voltage (V) Sine Wave + Voltage Step Input t2 4 6 8 10 12 14 16
1.5
2.5 3
3.5
4.5
Input voltage (V)
Output voltage (V)
Sine Wave + Voltage Step Input
Voltage Step Input V t
out dd C 1 in
tun f g

36. Autozeroing Floating-Gate Amplifier (AFGA)

37. Adaptive Diff-Pair Can be directly extended to: Multipliers / Mixers
“Bump” Circuits

38. Translinear Element using Floating-Gate Devices
Vdd
Iin
Iout C V1 V2 C
GND
GND