1. 3D technologies at Leti: Application to high energy CMOS sensors
Gabriel Parès
CEA LETI – Open 3D
Workshop INFIERI
21th of January, 2014

2. Outline Introduction: 3D at Leti Silicon interposers
Open3D and Medipix CMOS sensor application
Perspectives and conclusions

3. Introduction : Why do we need 3D Integration ?
To solve the following issues :
Form factor decrease :
X & Y axis
Z axis
Performances improvement
Decrease R, C, signal delay
Increase device bandwidth
Decrease power consumption
Heterogeneous integration
Integration of heterogeneous components
in the same system
Cost decrease
Si surface decrease
Reuse of existing Packaging,
BEOL & FEOL lines

4. About CEA-LETI 1,700 researchers Over 2,200 patents
French R&D institute in microelectronics & nanotechnologies from
1,700 researchers
Over 2,200 patents
250 M€ annual budget
50 start-ups & 365 industrial partners
Grenoble, France
~100 people working on 3D IC and 3D Packaging
Full 200mm & 300mm 3D capabilities

5. LETI - Open 3D™ organization
CEA
LETI
DCOS
Silicon components
DTSI
Silicon platform
DTBS
Biology and Health
DOPT
Imaging
DACLE
Design
3 Sections
SCME Components
SCMS MEMS-NEMS
S3D D Integration
4 Laboratories
LSA Substrate
LP3D 3D packaging
LECA Adv. die stacking
LCFC Reliability / characterization

6. Outline Introduction: 3D at Leti Silicon interposers
Coarse interposers
High density interposers
Thin silicon mechanical management
Open3D and Medipix CMOS sensor application
Perspectives and conclusions

7. Heterogeneous vs high density history
Silicon 3DIC
Side-by-side e-WLB
Density
>2010
e-WLB
high
Package-on-Package
Silicon interposer
>2011
>2005
WLP +IPD modules
Fan-in flip-chip
Embedded 3D-SiP
medium
>2005
Wirebond stack
FC-BGA
>2006
Low functionalities : single chip package (CSP), from wire bonding BGA to FP BGA and eWLB  higher density IO, larger die
Medium : more than 1 die in package, POP
High : SIP to Si interposer and Si3D
WB-BGA
Fan-in
>2000
low
2 chips FC
2D-SiP Heterogenous
low
medium
high
functionalities

8. High Density Interposer
2 ways of thinking “silicon interposer”
Coarse Interposers
Heterogeneous integration
Medium I/Os count
High flexibility
High Density Interposer
IC integration
Large I/Os count
Specific

9. High performance computing
2,5D: A “generic” solution?
High performance computing
FPGA
Mobile
3D Imaging
High-end servers
From Fujitsu
Passive /active
3D technology for tracker
<40µm pixels
Read out circuit at the back
Ultra fine routing at the interposer backside
PoP still there!!
Supply chain
5-10 Watts
Gbps
- 3D stack on interposer
- ~ W
4 levels of BE
20 Watts
28 Gbps
products
Under developement

10. 2000 - 2013: Leti 3D ‘generic’ technology toolbox
1 active layer
Face to Face
Face to back
3 level stack
Through Silicon Via
Die to Die
Die to Substrate
Handling
Die Placement
WL Molding
Temp. Bonding
(slide off)
High throuput
P&P
Thick Polymer
molding
Solder balls
Wire Bonding
TSV First
TSV Middle
& BS AR10
Temp Bonding
(Zonebond)
High precision
P&P
Thin Polymer
molding
Copper Pillars
Solder balls
TSV Last
AR1
Temp. bonding
(Peeling)
Thin Oxide
planarization
Self Assembly
µinserts
Copper pillar
TSV Last
AR2
Permanent
bonding
Wafer
To Wafer
DTW Cu-Cu
WLUF
µtubes
TSV Last
AR3
Classic
Underfill
Cu-Cu
TSV Last
High density

11. Bonding perm. or Temporary
Coarse interposer : the TSV last background
LETI transfer to ST Micro (2005  2008)
CMOS Imager sensor application
Through Silicon Via via-last Aspect Ratio 1 : 1
Cu liner
Vias last process
Production mode since 2009
300 mm production STM Crolles
FEOL - CMOS
BEOL
Bonding perm. or Temporary
(C2W or W2W)
Via formation
Back Side process

12. Today coarse interposers developments (2010 -2014):
Passive interposers
Active interposers
Medical applications
radar, military, space
Consumers
Fondamental physics
High perf. Passives (Capa 1µf/mm2)
Mmw platform:
Power amplifier (PA) 4G with TSV:
Particles detectors:
X-rays/particles dead zone free detectors
3x3 mm2
130nm SOI CMOS
60µm TSV
75µm TSV
6,5 x 6,5 mm2
60µm TSV
14x17mm2 detector, Medipix 130nm CMOS 60µm TSV
40% size decrease vs. organic
Passiv/activ
Die size
Techno node 130nm –TSV last

13. Lithography Stitching
High density interposer roadmap
65nm/65nm
Drivers: higher density, more I/O’s, more computing
Lithography Stitching
L/W 0.1um
Active interposer
100k I/Os
2,5D
45x45mm
Performance
60k I/Os
TSV-middle 5µm
35x35mm
TSV 10x100µm
L/W 0.5um
High performance computing market
3D Stepper
Investment
TSV-middle 10µm 3D
25x25mm
Year / size
2013
2014
2015
2016

14. Challenge: warpage control of large interposer
Example of flip-chip assembly of thinned FEI4 (ATLAS)
sensor
FEI4
7.3 x 10.9 mm2
20 x 18.9 mm2
Radiation hard  very thick BEOL
 Huge stress to control
From Fraunhofer IZM , T. Fritzsch ACES 2011

15. Protocol for stress compensation at Leti
Backside compensation layer deposition
Material development (Young modulus, CTE)
Wafer & die level stress optimization
30x30 mm2 test dies and FEI4 wafers tests on going
Glasgow University
Backside compensation layer
Materials tuning & model
Wafer level integration
Critical for very thin die (< 150 µ)
Max bow allowed for stacking
Die level bow monitoring
SiN
Topography and Deformation Measurement (TDM)
J. Charbonnier et al. EMPC 2013

16. Outline Introduction: 3D at Leti Silicon interposers
Open3D and Medipix CMOS sensor application
Perspectives and conclusions

17. Introduction to Open 3D™ platform
The concept :
Open 3D™ is a 3D technology offer, targeting industrial & academic customers
Key features :
Process of existing Si wafers: no re-design required
Light R&D investment : based on mature 3D technologies
Short cycle time
200 mm & 300 mm (2014)
Global offer from 3D design to component final packaging
Possibility to make proof-of-concept , prototyping & small volume production
Open 3D customer’s typology :
Laboratories, universities and international Institutions
Fabless
“Niche” markets manufacturers & integrators
IDM
Projects already
started with :
IDM integrated device manufacturer

18. Technological OPEN3DTM offer overview
Wafers (bottom and/or top dies) provided by costumer
Technological modules implemented by OPEN3DTM :
Through Silicon via (TSV)
Redistribution layer (RDL)
Under Bump Metallization (UBM)
Interconnections
Components stacking
Packaging with partner collaboration
OPEN3DTM inputs
Costumer inputs
Top dies wafer (provided by costumer)
Bumps
Micro-bumps
Micro pillars
Front side UBM
Back side UBM
wafer provided by costumer
TSV
Passivation
RDL
Pillars
BGA or package (provided by costumer or OPEN3D)

19. Wafer reception at LETI 3D Technology implementation
Technological OPEN3DTM offer overview
Wafer reception at LETI
Design & Layout
3D Technology implementation
TSV
Interconnections
Components stacking
Metalization
Open 3D™ wafer service
need identification
specifications on 3D
Packaging
Electrical Tests

20. X-Rays/Particles hybrid pixel detector application
CERN – LETI Project summary
Product : X-Ray hybrid pixel detector for medical applications
TSV last made in MEDIPIX wafers
Suppression of lateral wire bonding
Buttable sensor assembly
ROIC
CMOS pixel sensor
Medipix specifications
Design
Test structures
Wafer diameter: 200mm
Wafer thickness: ~725um
IC Technology: 130 nm / IBM
Top Surface: Al + Nitride
Chip size : x µm
TSV per chip: ~100
Process Flow
Wafer view
Single chip

21. Technological and electrical results
TSV Medipix3 results
 New lot with MEDIPIX RX running at LETI
Technology
RDL Cu 7 µm
Back side UBM
Medipix wafer after front side UBM
TSV 60µm x120µm
Accoustic image of the bonding interface
Thin wafer debonded on tape
Contact UBM
TSV:
Electrical Tests
Functionnal tests on ASICS
2 TSV chain resistance
TSV Last for Hybrid Pixel Detectors: Application to Particle Physics and Imaging Experiments
D. Henry(1), J. Alozy(2), A. Berthelot(1), R. Cuchet(1), C. Chantre(1), M. Campbell(2) ECTC 2013

22. On-Board Integration by Advacam
One TSV processed ROIC wafer diced and “good” chip candidates selected
Sn-Pb µ-solder balls were processed on Edgeless Sensor
μ-Solder bumping successfully done
Pixel pad on ROC
(after debonding of previous trials)
Sensor with Sn-Pb solder bumps
After reflow process
First Edgeless-TSV assembly
5 were provided to CERN in October 2013
SEM images courtesy of Advacam
Courtesy of Jerome ALOZY - CERN

23. Chip and assemblies mounting by CERN
BGA pads on the redistribution layer (back side of the chip) have been populated manually with low temperature solder balls
Chip soldering on the board by reflow in an oven
Bare chip with solder spheres
57Bi42Sn1Ag/Indalloy #282
PCB BGA footprint
First trial with a bare Medipix 3.1 chip
100 solder spheres of 0.635mm (after first reflow to attach them)
Courtesy of Jerome ALOZY - CERN
Courtesy of S. Kaufmann

24. First functional test Conditions Results
X-Ray chamber 35kV, 1mA
Hybrid Pixel Detector was positioned in front of the X-Ray beam
A biological sample (fish) placed before the detector
Results
First image was successful
The sensor bias current was high when applied through TSV compared to direct connection to sensor : possible reason are TSV insulation, leakage in assembly stack (humidity, bismuth solder balls)
First image obtained with a TSV processed hybrid pixel detector (flat field corrected)
Courtesy of Jerome ALOZY - CERN

25. Outline Introduction: 3D at Leti Silicon interposers
Open3D and Medipix CMOS sensor application
Perspectives and conclusions

26. Small volume production Small volume production
Open 3D™ : Technological roadmap
Technologies
Available for :
Fine pitch interco
Prototyping
Proof of concept
Available for :
TSV last shrinking
TSV Middle
Damascene RDL
Prototyping
Proof of concept
Available for :
TSV Last AR 3:1
Stacking D2W
Low temp Interco
Small volume production
Proof of concept
Prototyping
TSV Last AR 1:1 & 2:1
µbumps / µpillars
Bumps / pillars
UBM
Prototyping
Small volume production
2013
2014
2015
2016

27. What the next step in 3D? CMOS images sensor… once again
The market is ready and 3D WLP supply chains exist
3D stack of 2 partitioned dies
65nm processor reported below a 130nm image sensor
ANR 3D-IDEAS project
From, P. Coudrain et al. ECTC 2013

28. 3D imagers requires high density
Step 1 : 2-layer 3D imager (Back Side imager stacked on CMOS)
Leti objective : demonstration in 2014, technology in production in
Collaboration with ST
transistors
Back Side Imager
Hybrid Cu and SiO2, face-to-face, bonding
Pitch 5-10µm
CMOS
TSV (10µmx80µm), pitch 40µm
Solder bumps, connection to board (or interposer)
Step 2 : 3-layer 3D imager : detector on 2 CMOS layers
Leti objective : demonstration in , technology in production in
Consortium to be defined
Detector
Connection to detector, pitch 40µm
transistors
Hybrid Cu and SiO2, face-to-face, bonding, Pitch 5-10µm
Solder bumps, connection to board, interposer or 3D package

29. Key technology: Cu and SiO2 hybrid bonding
Bonding technology feasibility demonstrated
>90% yield obtained with daisy Chains with 30,000 3x3µm² Cu contacts
Contact resistance : 2,5 mΩ
Contact chain SEM cross section
Optical top view
Acoustic image of bonding
0.5 µm thick line
standard deviation σ ~ 1.2%
Resistance (Ω)
Full characterization of Cu/Cu direct bonding for 3D integration, Rachid Taibi, Léa Di Ciocciob et al., ECTC2010

30. Key technologies: ultra fine TSV
TSV last after bonding
High density 3D Flow:
Wafer to Wafer & Die to Wafer stacking
3µm diameter TSV via-last after bonding
Cu-Cu direct bonding
Permanent bonding W2W
Ultra fine pitch TSV
15µm

31. Main conclusions
Coarse and fine interposers offer already some credible alternative
Seen more like an evolution of packaging
Some benefits in ‘niche’ applications: medical, space, fundamental physics.
Strong challenges on the size of the modules
LETI is well positioned to offer 3D solutions for low volume applications
15 years of development work
A complete toolbox of process bricks
200/300 mm capabilities
Open 3D™ platform to address customer requests
3D integration for image sensors has long been introduced and will continue to be a main driving application
CMOS sensors, MEDIPIX and many other applications will continue benefiting from 3D
With higher density of integration as the next frontier

32. Thank you for attention
Main acknowlegements for this presentation:
Y. Lamy
D. Henry
G. Simon
P. Leduc
S. Chéramy
JC Souriau
Jf Teissier & E. Rouchouze
LETI Optronic Department’s colleagues
Shinko, IPDIA, ST, LETI’s partners…
Thank you for attention

33. Technical contact : yann.lamy@cea.fr
How to work with Open 3D™
Simple process for customer
Possible access to layout & Wafers through CMP
Tech. Specifications /
planning
Device layout
Wafers PO
Open 3D™ TechBox
Design & Layout
3D Technology
Tests
3D Packaging
Innovative product for your market
Markets
Technical contact :

34. TSV morphological & electrical results
TSV-last insight
TSV DRM & schematic
TSV Metal liner
Top metal
Dielectric liner
Metal 1
RDL
Passivation
Wafer size : & 300 mm
TSV type : via last / Cu liner
Minimum pitch : 80 µm (for 40µm TSV)
TSV diameter : 40 to 100 µm
Aspect Ratio (AR) : from 1:1 to 3:1
TSV morphological & electrical results
AR 1:1
AR 2:1
TSV characteristics
TSV geometry
R (mW)
C (pF)
Elec. Yield
Insul. (MW)
I leak (A)
TSV60 / 80
15.1
0.57
100 %
> 100 -
TSV60 / 120
19.1
0.82
1.3 10V
3.1 50V
TSV40 / 80
20.1
0.46
> 99%
TSV40 / 120
30.4
0.63
AR 3:1
Electrical tests
results