1. ARM Instructions I Prof. Taeweon Suh Computer Science Education Korea University

2. Korea Univ Data Processing Instructions Arithmetic instructions Logical instructions Comparison instructions Move instructions 2

3. Korea Univ Execution Unit in ARM 3 ALU Rn (1 st source) Barrel Shifter Rm Rd Pre-processing No pre-processing N (=shifter_operand) (2 nd source) Data processing instructions take 2 source operands: One is always a register. The other is called a shifter operand (either immediate or a register). If the second operand is a register, it can have a shift applied to it. Source: ARM Architecture Reference Manual

4. Korea Univ Arithmetic Instructions 4 ALU Rn Barrel Shifter Rm Rd N ADC add two 32-bit values with carryRd = Rn + N + carry ADD add two 32-bit valuesRd = Rn + N RSB reverse subtract of two 32-bit valuesRd = N - Rn RSC reverse subtract of two 32-bit values with carry Rd = N – Rn - !C SBC subtract two 32-bit values with carryRd = Rn - N - !C SUB subtract two 32-bit valuesRd = Rn - N Syntax: {cond}{S} Rd, Rn, N

5. Korea Univ ARM Arithmetic Instructions ARM Arithmetic instructions include add, adc, sub, sbc and some more  Check out the Architecture Reference Manual for the list of all arithmetic instructions 5 High-level code a = b + c ARM assembly code # R0 = a, R1 = b, R2 = c add R0, R1, R2 compile

6. Korea Univ Arithmetic Instructions – ADD ADD adds two operands, placing the result in Rd  Use S suffix to update conditional field  The addition may be performed on signed or unsigned numbers 6 ADD R0, R1, R2 ; R0 = R1 + R2 ADD R0, R1, #256 ; R0 = R1 + 256 ADDS R0, R2, R3,LSL#1 ; R0 = R2 + (R3 << 1) and update flags

7. Korea Univ add addr1, r2, r3 # r1 <= r2 + r3 7 ARM architect defines the opcode 1110binary hexadecimal0xe082 1003 0000 100000100001 0000 0011 1110 0 0 0010 0001 00000000 0011

8. Korea Univ Immediate 8-bit immediate field in ARM instructions limits values to the range of (0 ~ 255 (2 8 –1))  They are called immediates because they are immediately available from the instructions They do not require a register or memory access 8

9. Korea Univ add addr4, r5, #255 # r4 <= r5 + 255 9 ARM architect defines the opcode 1110binary hexadecimal0xe285 40ff 0010 0000 100001010100 1111 1110 1 0 0101 0100 0000 1111

10. Korea Univ Rm with Barrel Shifter 10 add r0, r1, r2, LSL #1 Shift Operation (for Rm)Syntax Immediate#immediate RegisterRm Logical shift left by immediateRm, LSL #shift_imm Logical shift left by registerRm, LSL Rs Logical shift right by immediateRm, LSR #shift_imm Logical shift right by registerRm, LSR Rs Arithmetic shift right by immediate Rm, ASR #shift_imm Arithmetic shift right by registerRm, ASR Rs Rotate right by immediateRm, ROR #shift_imm Rotate right by registerRm, ROR Rs Rotate right with extendRm, RRX Encoded here LSL: Logical Shift Left LSR: Logical Shift Right ASR: Arithmetic Shift Right ROR: Rotate Right RRX: Rotate Right with Extend add r0, r1, r2, LSL r3

11. Korea Univ Arithmetic Instructions – SUB SUB subtracts operand 2 from operand 1, placing the result in Rd  Use S suffix to update conditional field  The subtraction may be performed on signed or unsigned numbers 11 SUB R0, R1, R2 ; R0 = R1 - R2 SUB R0, R1, #256 ; R0 = R1 - 256 SUBS R0, R2, R3,LSL#1 ; R0 = R2 - (R3 << 1) and update flags

12. Korea Univ sub subr4, r5, #255 # r4 <= r5 - 255 12 ARM architect defines the opcode 1110binary hexadecimal0xe245 40ff 0010 0000 010001010100 1111 1110 1 0 0101 0100 0000 1111 ARM architect defines the opcode

13. Korea Univ Examples 13 Before: r0 = 0x0000_0000 r1 = 0x0000_0002 r2 = 0x0000_0001 SUB r0, r1, r2 After: r0 = 0x0000_0001 r1 = 0x0000_0002 r2 = 0x0000_0001 Before: r0 = 0x0000_0000 r1 = 0x0000_0005 ADD r0, r1, r1, LSL#1 After: r0 = 0x0000_000F r1 = 0x0000_0005

14. Korea Univ Examples 14 Before: cpsr = nzcv r1 = 0x0000_0001 SUBS r1, r1, #1 After: cpsr = nZCv r1 = 0x0000_0000 Why is the C flag set (C = 1)?

15. Korea Univ Logical Instructions 15 ALU Rn Barrel Shifter Rm Rd N AND logical bitwise AND of two 32-bit valuesRd = Rn & N ORR logical bitwise OR of two 32-bit valuesRd = Rn | N EOR logical exclusive OR of two 32-bit valuesRd = Rn ^ N BIC logical bit clearRd = Rn & ~N Syntax: {cond}{S} Rd, Rn, N

16. Korea Univ ARM Logical Instructions ARM logical instructions include and, orr, eor, bic Logical instructions operate bit-by-bit on 2 source operands and write the result to the destination register 16 High-level code a = b & c ; ARM assembly code # R0 = a, R1 = b, R2 = c and R0, R1, R2 compile

17. Korea Univ Logical Instructions – AND AND performs a logical AND between the two operands, placing the result in Rd  It is useful for masking the bits 17 AND R0, R0, #3 ; Keep bits zero and one of R0 and discard the rest

18. Korea Univ Logical Instructions – EOR EOR performs a logical Exclusive OR between the two operands, placing the result in the destination register  It is useful for inverting certain bits 18 EOR R0, R0, #3 ; Invert bits zero and one of R0

19. Korea Univ Examples 19 Before: r0 = 0x0000_0000 r1 = 0x0204_0608 r2 = 0x1030_5070 ORR r0, r1, r2 After: r0 = 0x1234_5678 Before: r1 = 0b1111 r2 = 0b0101 BIC r0, r1, r2 After: r0 = 0b1010

20. Korea Univ AND, OR, and EOR Usages and, or, nor  and is useful for masking bits Example: mask all but the least significant byte of a value: 0xF234012F AND 0x000000FF = 0x0000002F  or is useful for combining bit fields Example: combine 0xF2340000 with 0x000012BC: 0xF2340000 OR 0x000012BC = 0xF23412BC  eor is useful for inverting certain bits: Example: A EOR 3 20

21. Korea Univ Comparison Instructions 21 ALU Rn Barrel Shifter Rm Rd N CMN compare negatedFlags set as a result of Rn + N CMP CompareFlags set as a result of Rn – N TEQ test for equality of two 32- bit values Flags set as a result of Rn ^ N TST test bits of a 32-bit valueFlags set as a result of Rn & N Syntax: {cond}{S} Rn, N The comparison instructions update the cpsr flags according to the result, but do not affect other registers After the bits have been set, the information can be used to change program flow by using conditional execution

22. Korea Univ Comparison Instructions – CMP 22 CMP compares two values by subtracting the second operand from the first operand  Note that there is no destination register  It only update cpsr flags based on the execution result CMP R0, R1;

23. Korea Univ Move Instructions 23 ALU Rn Barrel Shifter Rm Rd N MOV Move a 32-bit value into a registerRd = N MVN Move the NOT of the 32-bit value into a registerRd = ~ N Syntax: {cond}{S} Rd, N

24. Korea Univ Move Instructions – MOV MOV loads a value into the destination register (Rd) from another register, a shifted register, or an immediate value  Useful to setting initial values and transferring data between registers  It updates the carry flag (C), negative flag (N), and zero flag (Z) if S bit is set C is set from the result of the barrel shifter 24 * SBZ: should be zeros MOV R0, R0; move R0 to R0, Thus, no effect MOV R0, R0, LSL#3 ; R0 = R0 * 8 MOV PC, R14; (R14: link register) Used to return to caller MOVS PC, R14; PC <- R14 (lr), CPSR <- SPSR ; Used to return from interrupt or exception

25. Korea Univ MOV Example 25 Before: cpsr = nzcv r0 = 0x0000_0000 r1 = 0x8000_0004 MOVS r0, r1, LSL #1 After: cpsr = nzCv r0 = 0x0000_0008 r1 = 0x8000_0004

26. Korea Univ Branch Instructions 26 B branchpc = label BL branch with link pc = label lr = address of the next instruction after the BL Syntax: B{cond} label BL{cond} label A branch instruction changes the flow of execution or is used to call a function  This type of instructions allows programs to have subroutines, if-then-else structures, and loops

27. Korea Univ B, BL B (branch) and BL (branch with link) are used for conditional or unconditional branch  BL is used for the subroutine (procedure, function) call  To return from a subroutine, use MOV PC, R14; (R14: link register) Used to return to caller Branch target address  Sign-extend the 24-bit signed immediate (2’s complement) to 30-bits  Left-shift the result by 2 bits  Add it to the current PC (actually, PC+8)  Thus, the branch target could be ±32MB away from the current instruction 27

28. Korea Univ Examples 28 B forward ADD r1, r2, #4 ADD r0, r6, #2 ADD r3, r7, #4 forward: SUB r1, r2, #4 backward: ADD r1, r2, #4 SUB r1, r2, #4 ADD r4, r6, r7 B backward BL my_subroutine CMP r1, #5 MOVEQ r1, #0 ….. My_subroutine: MOV pc, lr // return from subroutine

29. Korea Univ Memory Access Instructions Load-Store (memory access) instructions transfer data between memory and CPU registers  Single-register transfer  Multiple-register transfer  Swap instruction 29

30. Korea Univ Single-Register Transfer 30 LDR Load a word into a registerRd ← mem32[address] STR Store a word from a register to memoryRd → mem32[address] LDRB Load a byte into a registerRd ← mem8[address] STRB Store a byte from a register to memoryRd → mem8[address] LDRH Load a half-word into a registerRd ← mem16[address] STRH Store a half-word into a registerRd → mem16[address] LDRSB Load a signed byte into a register Rd ← SignExtend ( mem8[address]) LDRSH Load a signed half-word into a register Rd ← SignExtend ( mem16[address])

31. Korea Univ LDR (Load Register) 31 LDR loads a word from a memory location to a register  The memory location is specified in a very flexible manner with addressing mode // Assume R1 = 0x0000_2000 LDR R0, [R1] // R0 ← [R1] LDR R0, [R1, #16] // R0 ← [R1+16]; 0x0000_2010

32. Korea Univ STR (Store Register) 32 STR stores a word from a register to a memory location  The memory location is specified in a very flexible manner with a addressing mode // Assume R1 = 0x0000_2000 STR R0, [R1] // [R1] <- R0 STR R0, [R1, #16] // [R1+16] <- R0

33. Korea Univ Address Bus 0x0000 CPU Execution Example (ARM) 33 ARM CPU r0 r1 r2 r3 r13 r14 … 32 bits Register File R3 + Memory Data Bus add r2, r2, r3 ldr r3, [r13, 8] ldr r2, [r13, 4] 0x00220022 0x00110011 PC (r15) 0x0000 0x0004 0x0018 0x0014 0x0008 0x0004 0x0000 ldr r2, [r13, 4] ldr r3, [r13, 8] add r2, r2, r3 0x0014 0x00110011 0x00220022 0x0004 0x0018 0x0008 0x00220022 0x00110011 0x00330033 Assume that r13 contains 0x0010

34. Korea Univ Load-Store Addressing Mode 34 Indexing Method Data Base Address register updated? Example Preindex with writeback Mem[base + offset]Yes (Base + offset)LDR r0, [r1, #4]! Preindex Mem[base + offset]NoLDR r0, [r1, #4] Postindex Mem[base]Yes (Base + offset)LDR r0, [r1], #4 ! Indicates that the instruction writes the calculated address back to the base address register Before: r0 = 0x0000_0000 r1 = 0x0009_0000 Mem32[0x0009_0000] = 0x01010101 Mem32[0x0009_0004] = 0x02020202 After: r0 ← mem[0x0009_0004] r0 = 0x0202_0202 r1 = 0x0009_0004 LDR r0, [r1, #4]! LDR r0, [r1, #4] LDR r0, [r1], #4 After: r0 ← mem[0x0009_0004] r0 = 0x0202_0202 r1 = 0x0009_0000 After: r0 ← mem[0x0009_0000] r0 = 0x0101_0101 r1 = 0x0009_0004

35. Korea Univ (Assembly) Language There is no golden way to learn language You got to use and practice to get used to it 35

36. Korea Univ Backup Slides 36