1. Chapter 3 Manufacturing Wafers 半導體製程 材料科學與工程研究所 張翼 教授

2. Figure 3.1 Hydrogen reduction of trichlorosilane.

3. Figure 3.2 Unit cell of silicon.

4. Figure 3.3 GaAs crystal structure.

5. Figure 3.4 Poly- and single-crystal structures.

6. Figure 3.5 Crystal planes. are most widely used planes for Si.

7. Figure 3.6 Wafer orientation indicators. Si MOS devices Bipolar devices GaAs EPD: Etch Pit Density

8. Figure 3.7 Czochralski crystal-growing system. Seed and crucible are rotated in the opposite direction. Crucible (silica) CZ, LEC, FC: Three popular methods for growing wafers CZ is the most widely used method for Si Can also be N or P-type doped

9. Figure 3.8 Crystal growth from a seed. Heated to 1415 ℃ → Take 3 days to grow a crystal (12 inches are available now)

10. Figure 3.8 → surface tension

11. Figure 3.9 LEC system of crystal growth. Widely used for GaAs wafer Need B 2 O 3 to prevent As evaporation

12. Figure 3.10 Float-zone crystal-growing system. Low oxygen content Smaller diameter Higher dislocation density Used for Thyristors and Rectifiers

13. Figure 3.11 Comparison of CZ and float crystal-growing methods.

14. Figure 3.12 Vacancy crystal defect. Point defect Dislocations Growth defects: slip line twin

15. Figure 3.13 Crystal slip.

16. Figure 3.14 Crystal diameter grinding. Wafer were grown a few degrees off orientation for ion implantation or epi- growth

17. Figure 3.15 Crystal orientation determination. ORIENTATION DETERMINATION : X-ray diffraction Light reflection

18. Figure 3.16 Crystal flat grinding.

19. Figure 3.17 Wafer flat locations. Four point probe determine resistivity → doping conc. Hot point probe with polarity meter to detective polarity

20. Figure 3.18 Inside-diameter saw wafer slicing.

21. Figure 3.19 Laser dot coding (Reprinted from the Jan. 1998 edition of Solid State Technology, Copyright 1998 by PennWell Publishing Company.) Coding

22. Figure 3.20 Cross section of MOS transistor.

23. Figure 3.21 Abrasive and chemical-mechanical surface polishing. abrasion slurry lapping: remove surface damage from dicing CMP: slurry of silica with mild etchant (potassium/ammonium hydroxide) Alkaline slurry grow oxides and then mechanically removed.

24. Figure 3.21 rough polishing

25. Figure 3.21 CMP polishing

26. Figure 3.22 Trapping. Formed by sand blasting Backside damage → dislocation → trap of mobile ionic contamination (Gettering)

27. Figure 3.23 Wafer edge grinding.

28. Figure 3.24 Typical 200-mm wafer specification.