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UC San Diego / VLSI CAD Laboratory Reliability-Constrained Die Stacking Order in 3DICs Under Manufacturing Variability Tuck-Boon Chan, Andrew B. Kahng,

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Presentation on theme: "UC San Diego / VLSI CAD Laboratory Reliability-Constrained Die Stacking Order in 3DICs Under Manufacturing Variability Tuck-Boon Chan, Andrew B. Kahng,"— Presentation transcript:

1 UC San Diego / VLSI CAD Laboratory Reliability-Constrained Die Stacking Order in 3DICs Under Manufacturing Variability Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li VLSI CAD LABORATORY, UC San Diego

2 -2- Outline Motivation and Problem Statement Motivation and Problem Statement Modeling Modeling Our Methodologies Our Methodologies Experimental Setup and Results Experimental Setup and Results Conclusion Conclusion

3 -3- Outline Motivation and Problem Statement Motivation and Problem Statement Modeling Modeling Our Methodologies Our Methodologies Experimental Setup and Results Experimental Setup and Results Conclusion Conclusion

4 -4- Reliability Challenges for 3DICs Stacking of multiple dies increases power density  High power density  high temperature – –3DICs with four tiers increase peak temperature by 33°C Reliability (e.g., EM) highly depends on temperature Bottom tier Top tier (nearest to heat sink) 35°C Temperature range in a 5-tier 3DIC

5 -5- Context: Stacking of Identical Dies Identical dies in 3DIC stack   Can change stacking order Dies in stack can have different process corners, but must meet same performance spec  Adaptive Voltage Scaling (AVS)  each die has different V dd  Slower dies have higher V dd  power↑, temp↑, MTTF↓ Target frequency

6 -6- Motivation Stacking style: ordered selection of dies with particular process variations Heat sink  Letters S, T and F indicate the (slow, typical, fast) process corners  Strings over {S, T, F} indicate stacks (left-to-right corresponds to bottom-to-top) Stacking style “FTS” TSV MOSFET Fast-corner die Bottom tier MOSFET Slow-corner die Top tier TSV MOSFET Typical-corner die Middle tier

7 -7- Motivation Stacking style: ordered selection of dies with particular process variations  Different stacking style  different mean time to failure (MTTF)  Goal: find the optimal stacking style  improve reliability  Letters S, T and F indicate the (slow, typical, fast) process corners  Strings over {S, T, F} indicate stacks (left-to-right corresponds to bottom-to-top) Different stacking orders of {F, T, S} die  up to 44% ∆ MTTF

8 -8- Stacking Optimization Problem Given N dies with distinct process variation Such that frequency of each die in a stack = f req Objective to maximize summation of MTTFs of stacks

9 -9- Outline Motivation and Problem Statement Motivation and Problem Statement Modeling Modeling Our Methodologies Our Methodologies Experimental Setup and Results Experimental Setup and Results Conclusion Conclusion

10 -10- Reliability Model for 3DICs Electromigration is now a dominant reliability constraint   Our work focuses on EM We use Black’s equation to estimate MTTF of a die (MTTF die ) – –MTTF exponentially depends on temperature Failure rate ( λ ) is the number of units failing per unit time  During the useful-life period λ is constant  MTTF = 1 / λ (1)  Any failure of any die causes a stack to fail  λ stack = ∑ λ die (2)  (1) and (2)  MTTF stack = 1 / (∑1/MTTF die ) λ Time Useful-life period

11 -11- Bin-Based Model for Process Variation Each die exhibits distinct process variation   find the optimal stacking style is intractable We classify dies into constant number of process bins – –Dies with similar process variations are classified to one bin – –We assume same process variation for dies in one bin -3σ -1.5σ 0σ 1.5σ 3σ # of dies Bin 1Bin 2Bin 3

12 -12- Outline Motivation and Problem Statement Motivation and Problem Statement Modeling Modeling Our Methodologies Our Methodologies Experimental Setup and Results Experimental Setup and Results Conclusion Conclusion

13 -13- Determinants of 3DIC Reliability Peak temperature defines the MTTF of the 3DIC Two factors have significant impacts on temperature of 3DIC Process variation  Same performance requirement for all dies  Adaptive voltage scaling is deployed  Slower dies have higher V dd, power, higher temperatures Stacking order  Primary mechanism for thermal dissipation in a 3DIC is through heat sink  Vertical temperature gradient exists in 3DICs  Dies on bottom tiers have higher temperatures Worst-case peak temperature (= minimum MTTF) happens where slow dies are on bottom tiers (far from the heat sink)

14 -14- Rule-of-Thumb Rule-of-thumb: to optimize reliability of a 3DIC, the slowest dies should be located closest to the heat sink For a stack with particular composition of dies, the optimal stacking order is determined by rule-of-thumb  Letters {S, T, F} indicate process corners  Strings indicate stacking order Locating slow dies close to the heat sink helps improve MTTFs of 3DICs

15 -15- “Zig-zag” Heuristic Method Zig-zag heuristic method is based on rule-of-thumb Stack dies from slow to fast, from top tiers to bottom tiers Complexity of stacking optimization is NP-hard, but zig- zag is O(n·log(n)) (n = number of dies) Top tier (nearest to heat sink) Bottom tier

16 -16- ILP-Based Method ILP formulation – –Maximize ∑MTTF i ·C i – –Such that ∑C i ·Y q,i = X q // each input die should be used exactly once and consistent with its process bin C i ≥ 0 // number of output stacks implemented with i th stacking style cannot be negative Notations – –C i is the number of stacks implemented with i th stacking style – –MTTF i is the MTTF of stack implemented with i th stacking style – –Y q,i is the number of dies belong to q th bin contained in i th stacking style – –X q is the number of dies classified to q th bin

17 -17- Outline Motivation and Problem Statement Motivation and Problem Statement Modeling Modeling Our Methodologies Our Methodologies Experimental Setup and Results Experimental Setup and Results Conclusion Conclusion

18 -18- Experimental Setup Design: JPEG from OpenCores Technology: TSMC 65nm Libraries: characterized using Cadence Library Characterizer vEDI9.1 – –Process corner: SS, TT, FF – –Temperature: 45 ° C – 165 ° C – –Voltage: 0.9V – 1.2V LP solver: lp_solve 5.5 Thermal analysis: use Hotspot 5.02 – –Chip thickness = 50 μm – –Convection capacitance = 140.4J/K – –Ambient temperature = 60 ° C

19 -19- Improvement on MTTF Stacking optimization (ILP-based and zig-zag) increases the MTTFs of stacks Average MTTF of stacks

20 -20- Variation of MTTF Stacking optimization (ILP-based and zig-zag) increases the MTTFs of stacks Stacking optimization (ILP-based and zig-zag) reduces the variation in MTTFs ILP-based Zig-zag Greedy Random

21 -21- Variability Can Help ! Manufacturing variation can help improve MTTF of stacks

22 -22- Variability Can Help ! Manufacturing variation can help improve MTTF of stacks Supply voltage can exceed the maximum allowed value   Benefit from process variation disappears when the variation exceeds a particular amount Limited amount of process variation can help improve reliabilities of 3DICs with stacking optimization σ

23 -23- Outline Motivation Motivation Modeling Modeling Problem and Methodologies Problem and Methodologies Experimental Setups and Results Experimental Setups and Results Conclusion Conclusion

24 -24- Conclusion We study variability-reliability interactions and optimization in 3DICs We propose “rule-of-thumb” guideline for stacking optimization to reduce the peak temperature and increase MTTFs of 3DICs We propose ILP-based and zig-zag heuristic methods for stacking optimization We show that limited amount of manufacturing variation can help to improve reliabilities of 3DICs with stacking optimization Future Work – –Optimize on other objectives (power variation) – –Different performance requirements for dies

25 -25- Acknowledgments Work supported from Sandia National Labs, Qualcomm, Samsung, SRC and the IMPACT (UC Discovery) center

26 Thank You!

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