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Digital Circuits to Compensate for Energy Harvester Supply Variation Hao-Yen Tang David Burnett.

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Presentation on theme: "Digital Circuits to Compensate for Energy Harvester Supply Variation Hao-Yen Tang David Burnett."— Presentation transcript:

1 Digital Circuits to Compensate for Energy Harvester Supply Variation Hao-Yen Tang David Burnett

2 Energy-harvesting system Battery Solar cell TEG(Thermoelectric) RF coupling Problem: voltage ripple

3 Voltage ripple Energy Harvester On-chip Storage cap VLSI block Energy harvester-powered integrated system ~1nF Y. Ramadass and A. Chandrakasan, “A battery-less thermoelectric energy harvesting interface circuit with 35 mv startup voltage,” Solid-State Circuits, IEEE Journal of, vol. 46, no. 1, pp. 333–341, Jan. precharged

4 Possible solution Work with minimum voltage Supply regulation (with LDO) Modified basic cells (Razor) Dynamic clock period adjusting

5 Proposed solution Using a Delay-Lock Loop(DLL) to lock the clock period to critical path delay HW2 decoder circuit (4x cascaded)

6 Clock Generator (Voltage-Control Oscillator)

7 No crystal Ring oscillator Supply Sensitivity

8 Clock Generator (Voltage-Control Oscillator)

9 Critical Path duplica Extra delay result from simultaneous incoming signal Need to be reset every cycle 1 clock cycle measure 1 clock cycle reset

10 Clock Generator (Voltage-Control Oscillator)

11 PFD and loop filter Traditional PFD Charge pump with constant gm bias Second order loop filter for stability

12 Simulation result Supply Voltage VCO control signal Extra power overhead: 40.2uW (12.7% of the reference VLSI block)

13 Comparison table TechniqueThis work Supply regulation[2] Modified Basic Cell[3] Dynamic V DD adjusting[7] TopologyDynamically adjust clock period Fix the supply voltage with LDO Modify basic cells to detect errors Dynamically adjust clock period by adjusting analog supply voltage Hardware overhead 1 extra DLL 1 critical path duplica 1 LDOPeripheral circuits in each cell (proportional to VLSI block size) 1 LDO Main issue Response time Large percentage of power wasted in LDO Need to modify original VLSI block, hardware overhead proportional to VLSI block size Extra power line, power loss in LDO, need crystal to provide a reference clock

14 Acknowledgement Prof. Bora <3 EE241 classmates Dear teammate

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