1. Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process

2. Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Process

3. Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Circuit Under Design This two-inverter circuit (of Figure 3.25 in the text) will be manufactured in a twin-well process.

4. Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Circuit Layout

5. Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Process Flow These slides only present only a couple of snapshots of the manufacturing process for the circuits presented in the textbook. For a complete overview of all 62 steps, please refer to: http://tanqueray.eecs.berkeley.edu/~ehab/inv.html. Credits for these pictures go to Ehab Hakeem, Prof. Andrew Neureuther and the Simpl program.

6. Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Start Material Starting wafer: n-type with doping level = 10 13 /cm 3 * Cross-sections will be shown along vertical line A-A’ A A’

7. Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process N-well Construction (1) Oxidize wafer (2) Deposit silicon nitride (3) Deposit photoresist

8. Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process N-well Construction (4) Expose resist using n-well mask

9. Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process N-well Construction (5) Develop resist (6) Etch nitride and (7) Grow thick oxide

10. Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process N-well Construction (8) Implant n-dopants (phosphorus) (up to 1.5  m deep)

11. Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process P-well Construction Repeat previous steps

12. Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Grow Gate Oxide 0.055  m thin

13. Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Grow Thick Field Oxide Uses Active Area mask Is followed by threshold-adjusting implants 0.9  m thick

14. Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Polysilicon layer

15. Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Source-Drain Implants

16. Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Source-Drain Implants

17. Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Contact-Hole Definition (1) Deposit inter-level dielectric (SiO 2 ) — 0.75  m (2) Define contact opening using contact mask

18. Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Aluminum-1 Layer Aluminum evaporated (0.8  m thick) followed by other metal layers and glass

19. Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Advanced Metalization