1. PS/2 Mouse/Keyboard Port Discussion D7.2

2. PS/2 Port

3. PS/2 Port Timing The clock frequency must be in the range 10 - 16.7 kHz. Data sent from the device to the host is read on the falling edge of the clock signal. Data sent from the host to the device is read on the rising edge.

4. Summary: Bus States Data = high, Clock = high: Idle state. Data = high, Clock = low: Communication Inhibited. Data = low, Clock = high: Host Request-to-Send Device always generates the clock signal Data is transmitted one byte at a time Each byte is sent in a frame consisting of 11-12 bits. 1 start bit. This is always 0. 8 data bits, least significant bit first. 1 parity bit (odd parity). 1 stop bit. This is always 1. 1 acknowledge bit (host-to-device communication only)

5. Keyboard

6. Make and Break Codes Keyboard Scan Codes – Set 2 http://www.Computer-Engineering.org

7. Scan code = 15h (Q) PS/2 Port Timing ~25 KhZ clock

8. ----------------------------------------------------------------- -- Keyboard.vhd -- Demonstrate basic keyboard function ----------------------------------------------------------------- -- Author: Ken Nelson -- Copyright 2004 Digilent, Inc. ----------------------------------------------------------------- -- DESCRIPTION ----------------------------------------------------------------- -- Revision History: -- 06/14/04 (Created) KenN -- 07/01/04 (Optomized) DanP ----------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity keyboardVhdl is Port (CLK, RST, KD, KC: in std_logic; an: out std_logic_vector (3 downto 0); sseg: out std_logic_vector (6 downto 0)); end keyboardVhdl;

9. architecture Behavioral of keyboardVhdl is signal clkDiv : std_logic_vector (12 downto 0); signal sclk, pclk : std_logic; signal KDI, KCI : std_logic; signal DFF1, DFF2 : std_logic; signal shiftRegSig1: std_logic_vector(10 downto 0); signal shiftRegSig2: std_logic_vector(10 downto 1); signal MUXOUT: std_logic_vector (3 downto 0); signal WaitReg: std_logic_vector (7 downto 0); begin --Divide the master clock down to a lower frequency-- CLKDivider: Process (CLK) begin if (CLK = '1' and CLK'Event) then clkDiv <= clkDiv +1; end if; end Process; sclk <= clkDiv(12); -- 6.104 KHz 164 us period pclk <= clkDiv(3); -- 3.125 MHz 0.32 us period

10. --Flip Flops used to condition signals coming from PS2-- Process (pclk, clr, KC, KD) begin if(clr = '1') then DFF1 <= '0'; DFF2 <= '0'; KDI <= '0'; KCI <= '0'; else if (pclk = '1' and pclk'Event) then DFF1 <= KD; KDI <= DFF1; DFF2 <= KC; KCI <= DFF2; end if; end process; Filter clock and data signals from PS/2 port pclk KD DFF1 KDI pclk KC DFF2 KCI pclk <= clkdiv(3);-- 3.125 MHz0.32 us period

11. --Shift Registers used to clock in scan codes from PS2-- Process(KDI, KCI, RST) begin if (RST = '1') then ShiftRegSig1 <= "00000000000"; ShiftRegSig2 <= "0000000000"; else if (KCI = '0' and KCI'Event) then ShiftRegSig1(10 downto 0) <= KDI & ShiftRegSig1(10 downto 1); ShiftRegSig2(10 downto 1) <= ShiftRegSig1(0) & ShiftRegSig2(10 downto 2); end if; end process; ShiftRegSig1 ShiftRegSig2 KDI 1 10 0 0 D7D6D5D4D3D2D1D0P1 0 D7D6D5D4D3D2D1D0P1

12. --Wait Register process(ShiftRegSig1, ShiftRegSig2, RST, KCI) begin if(RST = '1')then WaitReg <= "00000000"; else if(KCI'event and KCI = '1' and ShiftRegSig2(8 downto 1) = "11110000")then WaitReg <= ShiftRegSig1(8 downto 1); end if; end Process; F0

13. MUXOUT <= WaitReg(7 downto 4) when sclk = '1' else WaitReg(3 downto 0); --Seven Segment Decoder-- sseg <="1000000" when MUXOUT = "0000" else "1111001" when MUXOUT = "0001" else "0100100" when MUXOUT = "0010" else "0110000" when MUXOUT = "0011" else "0011001" when MUXOUT = "0100" else "0010010" when MUXOUT = "0101" else "0000010" when MUXOUT = "0110" else "1111000" when MUXOUT = "0111" else "0000000" when MUXOUT = "1000" else "0010000" when MUXOUT = "1001" else "0001000" when MUXOUT = "1010" else "0000011" when MUXOUT = "1011" else "1000110" when MUXOUT = "1100" else "0100001" when MUXOUT = "1101" else "0000110" when MUXOUT = "1110" else "0001110" when MUXOUT = "1111" else "1111111"; --Anode Driver-- an(3) <= '1'; an(2) <= '1'; --disable first two 7-segment decoders. an(1 downto 0) <= "10" when sclk = '1' else "01"; end Behavioral;

14. Host-to-Device Communication

15. 1) Bring the Clock line low for at least 100 microseconds. 2) Bring the Data line low. 3) Release the Clock line. 4) Wait for the device to bring the Clock line low. 5) Set/reset the Data line to send the first data bit 6) Wait for the device to bring Clock high. 7) Wait for the device to bring Clock low. 8) Repeat steps 5-7 for the other seven data bits and the parity bit 9) Release the Data line. 10) Wait for the device to bring Data low. 11) Wait for the device to bring Clock low. 12) Wait for the device to release Data and Clock Host-to-Device Communication http://www.Computer-Engineering.org

16. Mouse Speed of mouse pressing left & right button sign overflow

17. http://www.ece.gatech.edu/academic/courses/fpga/Xilinx/ mouse.vhd source code