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Test and Verification Solutions116 th April 2010 Silicon South West, “Testing Times” The Economics of Verification Mike Bartley, TVS.

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Presentation on theme: "Test and Verification Solutions116 th April 2010 Silicon South West, “Testing Times” The Economics of Verification Mike Bartley, TVS."— Presentation transcript:

1 Test and Verification Solutions116 th April 2010 Silicon South West, “Testing Times” The Economics of Verification Mike Bartley, TVS

2 2 Test and Verification Solutions216 th April 2010 How can verification deliver value? What is verification? The economics of verification 100% verification is IMPOSSIBLE How to do verification successfully

3 3 Test and Verification Solutions316 th April 2010 The various RTL verification techniques Verification DynamicStatic Reviews Code Analysis FormalSimulation Emulation etc Dynamic Formal

4 4 Test and Verification Solutions416 th April 2010 Verification consumes the greatest design time Source: EE Times 2006 EDA Users Survey

5 5 Test and Verification Solutions516 th April 2010 Poor verification costs money in re-spins Source = Global IC (ASSP/ASIC) Service Management Report 2007, IBS 90nm6545 Functional20%22%26% Analog Mixed Signal 21%23%17% Reasons for respins Source: Aart de Geus, Chairman and CEO of Synopsys. Based on a survey of 2000 users by Synopsys “Half of all chip developments require a re-spin, three quarters due to functional bugs”, The 2004/2002 IC/ASIC Functional Verification Study by Collett International Research

6 6 Test and Verification Solutions616 th April 2010 Economic impact of Verification Inefficient verification –It is your biggest design task! –Delays to market Ineffective verification –Your biggest cause for re-spins (and recalls) Economics of early release –Better, faster verification –Tape-out early with measurable risk

7 7 Test and Verification Solutions716 th April 2010 Consider an adder –16 bits → 8.5 billion tests > 2500 years @ 1 test/second 2 x x 2 x x 2 y possible input conditions per transition Impossible to prove the absence of bugs Why is 100% verification impossible? Next State Logic Next State Logic Output Logic Output Logic Y X Z

8 8 Test and Verification Solutions816 th April 2010 What we want from verification Demonstrate absence of bugs Build confidence to ship the product –Defining measurable exit signoff criteria Demonstrate correctness of prioritised features Mitigate risk And stop when cost of further verification outweighs the advantages of increased confidence

9 9 Test and Verification Solutions916 th April 2010 Beginning verification earlier brings benefits A separate verification team enables this What usually happens? Design Verif Time Effort Design Verification Effort Time DesignVerification Time Effort Design Verification Effort Time

10 10 Test and Verification Solutions1016 th April 2010 Team independence in verification How hard does somebody try to break their own design? Verification engineers require different skills and attitudes Reconvergent paths (Bergeron 2000) Specification Interpretation RTL coding Verification Specification Interpretation RTL coding Verification Research shows this is the single biggest contributor to higher quality

11 11 Test and Verification Solutions1116 th April 2010 Good engineering principles delivers benefits Processes –Stable, clear specifications under change control –Configuration and defect management –Maximise re-use –Well defined signoff targets People –Verification engineers require different skill sets –Independence Appropriate tools and methodologies

12 12 Test and Verification Solutions1216 th April 2010 And what about software! 20% hardware, 80% software? Is the Toyota Prius recall the software equivalent of the Intel FPU bug?

13 13 Test and Verification Solutions1316 th April 2010 Summary About TVS About DVClub –“Design IP – help or hindrance to verification”, April 26th What is verification Why you should care Managing it mike@tandvsolns.co.uk Questions?


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