1. ECE web page  Courses  Course web pages
Introduction to VHDL
Course web page:
ECE web page  Courses  Course web pages
 ECE 545

2. Research and teaching interests:
Kris Gaj
Research and teaching interests:
reconfigurable computing
computer arithmetic
cryptography
network security
Contact:
Science & Technology II, room 223
(703)
Office hours: Monday, Wednesday 7:30-8:30 PM
and by appointment

3. MS in Computer Engineering
ECE 545
Part of:
MS in Computer Engineering
Required course in two concentration areas:
Digital Systems Design
Microprocessor and Embedded Systems
Elective course in the remaining concentration areas
MS in Electrical Engineering
Elective

4. Fall 2005 Enrollment as of August 31, 2005
MS in IS 1
PhD in IT 1
PhD in ECE 1
MS in CpE 13
MS in EE 12

5. Courses Design level Introduction to VHDL Computer Arithmetic VLSI
Automation
VLSI
Test Concepts
algorithmic
ECE
645
ECE
545
ECE
681
register-transfer
ECE
682
gate
ECE
586
transistor
Digital
Integrated
Circuits
ECE
699
layout
Mixed Signals VLSI
Semiconductor
Device Fundamentals
MOS Device
Electronics
ECE 584
ECE684
devices

6. Core courses There are TWO core courses common for all concentration
areas:
CS 571 Operating Systems – H. Aydin, S. Setia, C. Snow, project, C/C++ or Java
Pros:
Prerequisite for many other courses and projects
HLL (High Level Language) refresher
Offered regularly in Fall and Spring
ECE 548 Sequential Machine Theory – K. Hintz, R. Schneider
Common theoretical and mathematical foundation used in all
concentrations
Offered regularly in Spring
Not a strong prerequisite for any other course; can be taken any time
during the curriculum.

7. DIGITAL SYSTEMS DESIGN
Concentration advisor: Ken Hintz
1. ECE 545 Introduction to VHDL – K. Gaj, K. Hintz, projects, VHDL, Aldec/Synplicity/Xilinx and ModelSim/Synopsys
2. ECE 645 Computer Arithmetic: HW and SW Implementation – K. Gaj, projects, VHDL, Aldec/Synplicity/Xilinx and ModelSim/Synopsys
3. ECE 586 Digital Integrated Circuits – D. Ioannou
4. ECE 681 VLSI Design Automation – K. Kazi, projectz, VHDL, ModelSim/Synopsys

8. MICROPROCESSOR AND EMBEDDED SYSTEMS
Concentration advisor: Peter Pachowicz
ECE 511 Microprocessors – R. Barnes, P. Pachowicz,
ECE 545 Introduction to VHDL – K. Gaj, K. Hintz, project, VHDL, Aldec/Synplicity/Xilinx and ModelSim/Synopsys
ECE 611 Advanced Microprocessors – R. Barnes, D. Tabak
ECE 612 Real-Time Embedded Systems – K. Hintz

9. MICROPROCESSOR AND EMBEDDED SYSTEMS
Concentration advisor: Peter Pachowicz
ECE 511 Microprocessors – P. Pachowicz
ECE 545 Introduction to VHDL – K. Hintz, K. Gaj, project, VHDL, Aldec/ModelSim, Synplicity/Synopsys
ECE 611 Advanced Microprocessors – D. Tabak
ECE 612 Real-Time Embedded Systems – K. Hintz

10. Concentration Area Advisors
DIGITAL SYSTEMS DESIGN: Ken Hintz
COMPUTER NETWORKS: Brian Mark
NETWORK AND SYSTEM SECURITY: Kris Gaj
MICROPROCESSOR AND EMBEDDED SYSTEMS:
Peter Pachowicz

11. ECE 545 Lecture Projects Project 1 25 % Homework Project 2 10 % 10 %
Midterm exams
Midterm % in class
Midterm % take home

12. Lecture (1) Lecture 1 - Introduction to VHDL for Synthesis
Lecture 2 - Data Flow & Structural Modeling
of Combinational Logic. Packages and Components.
Lecture 3 – Behavioral Modeling of Sequential Logic.
Registers, Counters, Shift Registers.
Simple Testbenches.
Lecture 4 - Introduction to FPGA Devices & Tools
Lecture 5 - Finite State Machines
Lecture 6 - Algorithmic State Machines
Lecture 7 – Advanced Testbenches, File I/O, Memory
Lecture 8 - Mixed Style RTL Modeling
Lecture 9 - Advanced Examples: Sorting, Average, MAX, MIN
Midterm 1

13. Lecture (2) Lecture 10 - Variables, Functions and Procedures
Lecture 11 – ASIC Logic Synthesis with Synopsys
Design Compiler
Lecture 12 – Advanced Data Types. Operators and Attributes.
Lecture 13 - Timing. Event-Driven Simulation
Lecture 14 - Behavioral Modeling - The DLX Computer System
Midterm Exam 2

14. Textbooks Required Textbooks:
Volnei A. Pedroni, Circuit Design with VHDL,
The MIT Press, 2004
Sundar Rajan, Essential VHDL: RTL Synthesis Done Right,
S & G Publishing, 1998
Supplementary Textbooks:
Stephen Brown and Zvonko Vranesic,
Fundamentals of Digital Logic with VHDL Design,
2nd Edition, McGraw-Hill, 2005
Peter J. Ashenden, The Designer's Guide to VHDL,
2nd Edition, San Francisco:Morgan Kaufman, 1996, 2002

15. Midterm exam 1 2 hours 30 minutes in class design-oriented
open-books, open-notes
practice exams will be available on the web
Tentative date:
Wednesday, October 26th

16. Saturday, Sunday, December 10-11
Midterm Exam 2
take-home
full design, including logic synthesis and timing analysis
with Synopsys Design Compiler
48 hours
Tentative date:
Saturday, Sunday, December 10-11

17. Project technologies FPGA: Field Programmable Gate Arrays and
ASIC: semi-custom Application Specific Integrated Circuits

18. World of Integrated Circuits
Full-Custom
ASICs
Semi-Custom
ASICs
User
Programmable
PLD
FPGA
PAL
PLA
PML
LUT
(Look-Up Table)
MUX
Gates

19. Two competing implementation approaches
FPGA
Field Programmable
Gate Array
ASIC
Application Specific
Integrated Circuit
designs must be sent
for expensive and time
consuming fabrication
in semiconductor foundry
bought off the shelf
and reconfigured by
designers themselves
no physical layout design;
design ends with
a bitstream used
to configure a device
designed all the way
from behavioral description
to physical layout

20. Which Way to Go? ASICs FPGAs Off-the-shelf High performance
Low development cost
Low power
Short time to market
Low cost in
high volumes
Reconfigurability

21. What is an FPGA Chip ? Field Programmable Gate Array
A chip that can be configured by user to implement different digital hardware
Configurable Logic Blocks and Programmable Switch Matrices
Bitstream to configure: function of each block & the interconnection between logic blocks
I/O Block
“FPGAs are the reconfigurable top of the shelf chips. Reconfiguration technique is very similar to SRAM approach.”
The FPGA architectures consist of CLBs and Programmable Switch Matrices (PSMs). The gates are placed inside CLBs in FPGAs. These info will be supported by the next slide as well.
Bullet 3 is not very correct. Because FPGA is not a large array of gates with programmable interconnections. As I have mentioned above, the main power of FPGAs come from CLB and its internal components like LUTs(look up tables), Carry bit Logics, Gates, FFs(Flip Flops) and MUXs(multiplexors).
Source: [Brown99]

22. CLB Structure
The configurable logic block (CLB) contains two slices. Each slice contains two 4-input look-up tables (LUT), carry & control logic and two registers. There are two 3-state buffers associated with each CLB, that can be accessed by all the outputs of a CLB.
Xilinx is the only major FPGA vendor that provides dedicated resources for on-chip 3-state bussing. This feature can increase the performance and lower the CLB utilization for wide multiplex functions. The Xilinx internal bus can also be extended off chip.

23. CLB Slice SLICE Carry & Control Logic Carry & Control Logic
COUT YB
Look-Up
Table
Carry
&
Control
Logic Y G4 G3 G2 G1 S D Q O CK EC R
F5IN BY SR XB
Look-Up
Table
Carry
&
Control
Logic X S F4 F3 F2 F1 D Q O
The configurable logic block (CLB) contains two slices. Each slice contains two 4-input look-up tables (LUT), carry & control logic and two registers. There are two 3-state buffers associated with each CLB, that can be accessed by all the outputs of a CLB.
Xilinx is the only major FPGA vendor that provides dedicated resources for on-chip 3-state bussing. This feature can increase the performance and lower the CLB utilization for wide multiplex functions. The Xilinx internal bus can also be extended off chip. CK EC R
CIN
CLK CE
SLICE

24. LUT (Look-Up Table) Functionality
Look-Up tables are primary elements for logic implementation
Each LUT can implement any function of 4 inputs

25. Major FPGA Vendors SRAM-based FPGAs Xilinx, Inc. Altera Corp. Atmel
Lattice Semiconductor
Flash & antifuse FPGAs
Actel Corp.
Quick Logic Corp.
Share over 60% of the market

26. Xilinx FPGA Families Old families XC3000, XC4000, XC5200
old 0.5µm, 0.35µm and 0.25µm technology. Not recommended for modern designs.
Low-cost families
Spartan/XL – derived from XC4000
Spartan-II – derived from Virtex
Spartan-IIE – derived from Virtex-E
Spartan-3
High-performance families
Virtex (0.22µm)
Virtex-E, Virtex-EM (0.18µm)
Virtex-II, Virtex-II PRO (0.13µm)
Virtex-4 (0.09µm)

27. Design process (1) Specification
Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds…..
VHDL description (Your VHDL Source Files)
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RC5_core is
port(
clock, reset, encr_decr: in std_logic;
data_input: in std_logic_vector(31 downto 0);
data_output: out std_logic_vector(31 downto 0);
out_full: in std_logic;
key_input: in std_logic_vector(31 downto 0);
key_read: out std_logic; );
end AES_core;
Functional simulation
Synthesis
Post-synthesis simulation

28. Design process (2) Implementation (Mapping, Placing & Routing)
Timing simulation
Configuration
On chip testing

29. Design Process control from Active-HDL

30. Simulation Tools
Many others…

33. Logic Synthesis VHDL description Circuit netlist
architecture MLU_DATAFLOW of MLU is
signal A1:STD_LOGIC;
signal B1:STD_LOGIC;
signal Y1:STD_LOGIC;
signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;
begin
A1<=A when (NEG_A='0') else
not A;
B1<=B when (NEG_B='0') else
not B;
Y<=Y1 when (NEG_Y='0') else
not Y1;
MUX_0<=A1 and B1;
MUX_1<=A1 or B1;
MUX_2<=A1 xor B1;
MUX_3<=A1 xnor B1;
with (L1 & L0) select
Y1<=MUX_0 when "00",
MUX_1 when "01",
MUX_2 when "10",
MUX_3 when others;
end MLU_DATAFLOW;

34. Synthesis Tools
… and others

35. Features of synthesis tools
Interpret RTL code
Produce synthesized circuit netlist in a standard EDIF format
Give preliminary performance estimates
Some can display circuit schematics corresponding to EDIF netlist

36. Implementation
After synthesis the entire implementation process is performed by FPGA vendor tools

38. Mapping
LUT0
LUT4
LUT1
FF1
LUT5
LUT2
FF2
LUT3

39. Placing
FPGA
CLB SLICES

40. Routing
FPGA
Programmable Connections

41. Design Process control from Active-HDL

42. Top Level ASIC Digital Design Flow
Design Inception
RTL Design
Synthesis
Macro Development
Place +
Route
Physical Verification
Design Complete

43. RTL Design Design Function Digital Tool Design Inception
Cadence NC Verilog
Mentor Graphis ModelSim
Lint Checking (
users discression)
Cadence Hal
FPGA Verification (
users discression)
Xilinx ISE
Code Coverage (
users discression)
Cadence ICT
Testbench Developement
Cadence NC Verilog
Mentor Graphics ModelSim
Mixed Mode Simulation
Cadence AMS Designer
Formal Verification
Cadence Conformal
System Interface Simulation
Agilent ADS
Synthesis
Matlab
Synthesis +
Macro
Synthesis +
Macro
Development
Development

44. Synthesis + Macro Development
Design Function
Digital Tool
RTL
RTL
Synthesis
Macro Generation
Synopsys DC
Cadence RC
Artisan
DFT
Macro Verification
Synopsys DFT Compiler
Cadence RC
Mentor Graphics Calibre
Macro Rules Generation /
Static Timing Analysis
Synopsys PrimeTime
Artisan /
Library Generation
Cadence DFII
Logical Equivalency
Cadence Conformal
Verification
Verification
Gate -
Level Simulation
Cadence NC Verilog
Mentor Graphics Modelsim
Place +
Route
Place +
Route

45. Place + Route Design Function Digital Tool Synthesis Synthesis
Floorplan
Macro Placement /
Std Cell
Placement
Cadence Encounter
Placement -
Based
Optimization
Clock Tree Synthesis
Static
Timing
Synopsys
Analysis
Prime -
Time
Route
Cadence NanoRoute
Spare Cells /
Decoupling
ATPG
Mentor Graphics
Cap Filler Cells
FastScan
Cadence Encounter
RC Extraction
Cadence Fire
&
Ice QX
Signal Integrity
Cadence CeltIC /
Voltage
Storm
Metal Fill
Cadence Encounter
Verification
Verification

46. Physical Verification
Design Function
Digital Tool
Placed +
Routed
Placed +
Routed
Design
Design
GDSII Preparation /
Simulation Preparation
Cadence DFII
Cadence DFII
Schematic Preparation
Back Annotated Simulation
Layout
Chip Finishing
Cadence Virtuoso
Cadence NC Verilog
DRC
LVS
Mentor Graphics Calibre
ERC
Synopsys Nanosim
Top -
Level Simulation
Cadence AMS Designer
Design Complete
Design Complete

47. CAD software available at GMU (1)
VHDL simulators
Aldec Active-HDL (under Windows)
available in the FPGA Lab, S&T II, room 203
student edition can be purchased on an individual
basis ($ S&H)
ModelSim (under Unix)
available from all PCs in the ECE educational labs
using an X-terminal emulator
available remotely from home using a fast Internet
connection

48. CAD software available at GMU (2)
Tools used for logic synthesis
FPGA synthesis
Synplicity Synplify Pro (under Windows)
Xilinx XST (under Windows)
available in the FPGA Lab, S&T II, room 203
ASIC synthesis
Synopsys Design Compiler (under Unix)
available from all PCs in the ECE educational labs
using an X-terminal emulator
available remotely from home using a fast Internet
connection

49. CAD software available at GMU (3)
Tools used for implementation (mapping, placing
& routing) in the FPGA technology
Xilinx ISE (under Windows)
available in the FPGA Lab, S&T II, room 203

50. Projects – Overview
Project 1 (25 points) mid-September – October (~6 weeks)
Application: cryptography OR digital signal processing
Technology: FPGA
Target: synthesizable code, timing, resource usage
Project 2 (10 points) November (~3 weeks)
Application: the same as in Project 1
Technology: ASIC
Target: revised synthesizable code, synthesis scripts,
timing, resource usage, comparison
Project 3 (15 points) December (~3 weeks)
Application: simple microprocessor/microcontroller
Target: behavioral code

51. Projects 1, 2 choice between two project topics
cryptography (e.g., encryption, authentication, hash)
digital signal processing (e.g., digital filter, FFT,
image processing, etc.)
both topics specified by the instructor
initial specification in the form of a
- pseudocode and/or flowchart
- detailed interface
design and source code is required to be scalable,
i.e., work for different parameters and operand sizes,
specified at the time of synthesis

52. Example: Last year’s project - RC5 cipher
Encryption
Decryption
A || B = M
A = A + S[0]
B = B + S[1]
for i= 1 to r do {
A= (AB) <<< B + S[2i]
B= (BA) <<< A + S[2i+1] }
C= A || B
A || B = C
for i= r downto 1 do {
B= ((BS[2i+1]) >>> A)  A
A= ((A  S[2i])>>>B)  B }
B = B  S[1]
A = A  S[0]
M= A || B

53. Encryption/decryption
clock
Encryption/decryption
unit
reset
encrypt/decrypt
data output m n
data input
data available
write
full
data read
round number
round key(s)
Key memory
cycle number
round key(s) k
key input
Key scheduling unit
key available
key read

54. Projects 1, 2 Optimization Criteria
Maximum ratio
Throughput / Circuit Area or
Minimum product
Latency  Circuit Area

55. Primary timing parameters
Latency
Throughput
Xi+2 Xi
Xi+1 Xi
Time to
process
a single block
of data
Circuit
Circuit
Number of bits
processed
in a unit of time
Yi+2 Yi
Yi+1 Yi
Block_size · Number_of_blocks_processed_simultaneously
Throughput =
Latency

56. Project 3 from FALL 2004 to be modified in FALL 2005

57. System to be implemented
Using high-level behavioral VHDL describe
an 8-bit microcontroller MC68HC11E9, working
in a single-chip mode, with the following
simplifications:
Inputs and outputs of the microcontroller are reduced to
clk, reset, PORTB, and PORTC.
Internal registers are reduced to the registers
A, B, SP, CC (Condition Codes NZVC), and PC.
Internal I/O registers are limited to
PORTB at the memory address $1004
PORTC at the memory address $1003
DDRC at the memory address $1007

58. 4. Instruction set of the microcontroller is reduced
to the following instructions
Data transfer instructions
LDAA, LDAB, LDS, STAA, STAB, STS
Arithmetic instructions
ADDA, ADDB, SUBA, SUBB
Logic instructions
ANDA, ANDB, ORAA, ORAB, EORA, EORB
Data test instructions
CMPA, CMPB
Control instructions
BEQ, BNE, BSR, RTS
Stack instructions
PSHA, PSHB, PULA, PULB

59. 5. Addressing modes of the microcontroller are reduced
to the following modes
a. immediate
b. extended
c. inherent
d. relative
6. Program is stored in the internal ROM starting at the
address $D000
7. After reset, PC is set to the address $D000.
8. The only parts of 68HC11E9 implemented in your
model are:
a. CPU
b. RAM (512 B in the range $0000-$01FF)
c. ROM (12 kB in the range $D000-$FFFF)
d. parallel I/O (PORTB and PORTC)

60. Features of the model
Your model should allow cycle accurate modeling
of the circuit behavior.
2. Your model should contain debugging features
equivalent to the debugging features of the DLX model,
discussed in class and described in Ashenden, Chapter 15.
3. Generic parameters passed to the model
should include
a. name of the file with the contents of the internal ROM
b. clk-to-output delay
c. debugging mode
Your model should report all undefined opcodes,
treat them as NOP, and proceed to the next ROM address.

61. Testing and debugging
The behavior of your model should be carefully verified
using a testbench instantiating your model with
a. the internal ROM containing a valid program
composed of a substantial subset of instructions
implemented in the model
b. debugging mode set to the most detailed mode
(trace_each_step)

62. Deliverables
All source code files.
Contents of the internal ROM used for
the model verification, in the hexadecimal notation, and
expressed using the corresponding 68HC11
assembly language mnemonics.
The detailed log/report generated by your model
for a given contents of ROM, and with the debugging
mode set to trace_each_step.

63. All Projects - Organization
Projects divided into phases
Intermediate code submitted through WebCT at selected checkpoints and evaluated by the instructor and/or TA
Penalty points for falling behind the schedule (below 50% of the work that supposed to be done by a certain deadline)
Feedback provided to students on a fair and best effort basis
Final report and codes submitted by WebCT and graded using a full scale
Contest for the best results (bonus points awarded to the winners)
Penalty and bonus points added to the final grade

64. Honor Code Rules
All students are expected to write and debug their codes individually
Students are encouraged to help and support each other in all problems related to the - operation of the CAD tools, - basic understanding of the problem.