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D Flip-Flops Objectives
Explain the operation of D flip-flops Understand how reset and preset inputs can be added to any flip-flop Generate the next state equations and state tables for all types of flip-flops ECEn 224 Winter 2002 February 15, 2002
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Set to the state of the D input on clock transition
D Flip-Flops Set to the state of the D input on clock transition CK Q’ denotes a clock input denotes transition on high to low Flip Flop Q D ECEn 224 Winter 2002 February 15, 2002
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Set to the state of the D input on clock transition
D Flip-Flops Set to the state of the D input on clock transition CK Q’ Flip Flop Q D Q+ = D ECEn 224 Winter 2002 February 15, 2002
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D Flip-Flops D Q Clock ECEn 224 Winter 2002 Q’ Q D time CK Flip Flop
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D Flip-Flops (Typical)
ECEn 224 Winter 2002 February 15, 2002
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D Flip-Flop P P’ Q Q’ Clock ECEn 224 Winter 2002 time D=0 1 1 1 1 1
1 1 1 1 1 = 0 time Clock P P’ Q Q’ ECEn 224 Winter 2002 February 15, 2002
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D Flip-Flop P P’ Q Q’ Clock ECEn 224 Winter 2002 time D=0 1 1 1 1 1
1 1 1 1 1 01 time Clock P P’ Q Q’ ECEn 224 Winter 2002 February 15, 2002
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D Flip-Flop P P’ Q Q’ Clock ECEn 224 Winter 2002 time D=0 1 10 01 1
1 10 01 1 1 1 01 time Clock P P’ Q Q’ ECEn 224 Winter 2002 February 15, 2002
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D Flip-Flop P P’ Q Q’ Clock ECEn 224 Winter 2002 time D=0 1 10 01 1
1 10 01 1 10 10 1 time Clock P P’ Q Q’ ECEn 224 Winter 2002 February 15, 2002
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D Flip-Flop P P’ Q Q’ Clock ECEn 224 Winter 2002 time D=0 1 1 1 10 1
1 01 1 1 10 10 1 time Clock P P’ Q Q’ ECEn 224 Winter 2002 February 15, 2002
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D Flip-Flop P P’ Q Q’ Clock ECEn 224 Winter 2002 time D=0 1 1 1 1 01
1 01 1 1 1 time Clock P P’ Q Q’ ECEn 224 Winter 2002 February 15, 2002
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D Flip-Flop P P’ Q Q’ Clock ECEn 224 Winter 2002 time D=0 1 1 1 1 1
1 1 1 1 1 time Clock P P’ Q Q’ ECEn 224 Winter 2002 February 15, 2002
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D Flip-Flop P P’ Q Q’ Clock ECEn 224 Winter 2002 time D=0 1 1 1 1 10
1 1 1 1 10 time Clock P P’ Q Q’ ECEn 224 Winter 2002 February 15, 2002
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D Flip-Flop P P’ Q Q’ Clock ECEn 224 Winter 2002 time D=0 1 1 01 1
1 1 01 1 10 10 time Clock P P’ Q Q’ ECEn 224 Winter 2002 February 15, 2002
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D Flip-Flop P P’ Q Q’ Clock ECEn 224 Winter 2002 time D=0 01 1 1 01
1 1 01 1 10 time Clock P P’ Q Q’ ECEn 224 Winter 2002 February 15, 2002
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D Flip-Flop P P’ Q Q’ Clock ECEn 224 Winter 2002 time D=0 01 10 1 1
1 1 1 time Clock P P’ Q Q’ ECEn 224 Winter 2002 February 15, 2002
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D Flip-Flop P P’ Q Q’ Clock ECEn 224 Winter 2002 time D=0 1 10 1 1 1
1 1 1 01 time Clock P P’ Q Q’ ECEn 224 Winter 2002 February 15, 2002
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D Flip-Flop P P’ Q Q’ Clock ECEn 224 Winter 2002 time D=0 1 1 1 1 01
1 1 1 01 time Clock P P’ Q Q’ ECEn 224 Winter 2002 February 15, 2002
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D Flip-Flop P P’ Q Q’ Clock ECEn 224 Winter 2002 time D=0 1 1 1 1 1
1 1 1 1 time Clock P P’ Q Q’ ECEn 224 Winter 2002 February 15, 2002
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D Flip-Flop with Reset Input
A reset or clear input is added to many flip-flops for convenience This overrides other inputs and forces Q to 0 indicates that the reset is active low (reset on CLR = 0) Q’ Q Clear CLR CK D ECEn 224 Winter 2002 February 15, 2002
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J-K Flip-Flop with Reset and Preset
A preset line is added to force a flip-flops to Q = 1 This overrides other inputs Clear and preset should not be active at the same time Q’ Q This J-K flip-flop operates normally CLR = 1 and PRE = 0 Clear CLR PRE CK K J ECEn 224 Winter 2002 February 15, 2002
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Flip-Flop Registers Flip-flops are grouped to form data registers
Clear and preset are for designer convenience in initializing registers Data Out Q 1 Q 2 Q 3 Q 4 Q’ Q Q’ Q Q’ Q Q’ Q CLR CLR CLR CLR CK CK CK CK D D D D Clock Clear D 1 D 2 Data In D 3 D 4 ECEn 224 Winter 2002 February 15, 2002
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Characteristic Equations
Set-Reset Trigger J-K D Q+ = D Q+ = T Q Q+ = TQ’ + Q’T Q+ = JQ’ + K’Q Q+ = S + R’Q (SR = 0) § Inputs not allowed ECEn 224 Winter 2002 February 15, 2002
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Summary Explain the operation of D flip-flops
Understand how reset and preset inputs can be added to any flip-flop Generate the next state equations and state tables for all types of flip-flops ECEn 224 Winter 2002 February 15, 2002
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