1. Test #2 Combinational Circuits – MUX Sequential Circuits – Latches – Flip-flops – Clocked Sequential Circuits – Registers/Shift Register – Counters – Memory

2. Multiplexer 2-to-1 mux 4-to-1 mux

3. 2-to-1 mux A 2-input mux is controlled by a single control line s. If s=0, y=a and y=b if s=1.

4. Implementation

5. 4-to-1 Mux

6. (Creating a 4 x 1 MUX from 2 x 1 MUX)

7. Latches Latches are level sensitive. Latches propagate values from input to output continuously. S sets Q =1; R sets Q=0 – Active low inputs are enabled by 0s. – Active high inputs are enabled by 1s.

8. SR Latch with NOR Gates t PDSQ =2 NOR gate delays. t PDRQ_ =1 NOR gate delay Forbidden State SR are trigger pulses which can return to zero once Q is set. Active High inputs

9. Typical Mode of Operation 1.Both inputs of the latch remain at 0 unless the state has to be changed. 2.When both S and R are equal to 0, the latch can be in either the set or the reset, depending on which input was most recently a 1. S must go back to 0 in order to avoid S=R=1. Q and Q’ do not change states when S goes back to 0. R must go back to 0 in order to avoid S=R=1. Q and Q’ do not change states when R goes back to 0.

10. SR Latch with NAND Gates 1.Both inputs of the latch remain at 1 unless the state has to be changed. 2.When both S and R are equal to 1, the latch can be in either the set or the reset, depending on which input was most recently a 1. R must go back to 1 in order to avoid S=R=0. Q and Q’ do not change states when R goes back to 1. S must go back to 1 in order to avoid S=R=0. Q and Q’ do not change states when S goes back to 1.

11. Comparison (activated with a 1) (activated with a 0)

12. SR Latch with NAND Gates Active low inputs

13. SR latch with Control Line (En=0) 1. En=0, Q and Q’ will not be changed! 0 1 1

14. SR latch with Control Line (En=1) 1.En=1, Q and Q’ will be affected by S and R. 2.We now have active-high enabled circuit! 1 S’ R’

15. D Latch

16. D Latch (En=0) 0 1 1

17. D Latch (En=1) 1 D’ D Q follows D as long as En is asserted (En=1). Data is temporary stored when En is 0.

18. D-latch Operation

19. D-Latch (CK=0) 0 D DB 0 0

20. D-Latch (CK=1) 1 D DB D D

21. Analyze D Latch Using Boolean Algebra

22. D Flip-Flop

23. Negative Edge triggered D Flip-Flop Clk=0 0 1 Q=Y hold

24. Negative Edge triggered D Flip-Flop Clk=1 1 0 Y=D hold

25. Negative Edge Triggered D Flip- Flop CK of latch 1 CK of latch 2 OUT=X Y=D 2: Hold 1: Track 1:hold 2:track 1 2 1:hold 2:track Q=Y Not enough time for D→Y →Q Q will hold steady The value that is produced at the output of the flip-flop is the value that was stored in master stage immediately before the negative edge Occurred.

26. Positive Edge D-Flop 1 2 CK of latch 2 CK of latch 1 X X=IN OUT=X 1: Hold 2: Track 2:hold 1:track 2:hold 1:track

27. D-Type Positive Edge Triggered Flip-Flop (CLK=0) 0 0 1 1 CLK =0, maintain the present state

28. D-Type Positive Edge Triggered Flip-Flop 0 0→ 1 1 1 → 0 Q changes 01 1 0 D=0 as Clk=0→ 1

29. D-Type Positive Edge Triggered Flip-Flop 1 0→ 1 1 → 0 1 → 1 Q changes 10 0 1 D=1 as Clk=0→ 1

30. D-Type Positive Edge Triggered Flip-Flop 0 → 1 1 S The flip-flop is unresponsive to changes in D 1 1 D=0→ 1 as Clk=1 S’ Please explore different possible value of S on your own. This will work even for S=R=1 and S=R=0.

31. Symbol of D Flip-Flops

32. Analysis of Clocked Sequential Circuits

33. Example of a Sequential Circuit D flip-flops

34. Example: Start with A=0, B=0, x=0. A(next)=0 B(next)=0 Y(next)=0

35. What are A(next), B(next) and y(next) given that A=1, B=1 and X=1? D flip-flops

36. Alternate State Table

37. State Diagram Each circle is a state When x=1, y=0.

38. State Diagram Each circle is a state When x=0, y=1.

39. Detects 0 in the bit stream of data Output is a 0 as long as input is a 1. The first 0 after a string of 1 transfers the circuit back to 00.

40. Summary

41. Shift Register

42. Register A register is a group of flip-flops, each one of which is capable of storing one bit of information. Issues: – You do not have an option hold the output when you don’t want to outputs updated. 4 D flip-flops=4 bits of storage=4-bit register

43. 4-bit Register with Parallel Load Control

44. Load=“1”→Update “1” “0” “1” “I 0 ” I 0 is fed to DFF when Load is a 1.

45. Load=“0”→Hold! “0” “1” “A 0 ” “0” “A 0 ” A 0 is fed to DFF when Load is a 0. So the output is holding!

46. Four Bit Shift Register 123 4 Q of DFF1 gets SI after the first rising edge of the CLK Q of DFF2 gets SI after the second rising edge of the CLK Q of DFF3 gets SI after the third rising edge of the CLK Q of DFF4 gets SI after the fourth rising edge of the CLK

47. Block Diagram of a Universal Shift Register This is called the universal shift register because it has both shifts and parallel load capabilities.

48. Detail Implementation

49. Four-to-one-line Mux

50. Mode Control

51. S0=0, S1=0 [No Change Mode] S0=0, S1=0

52. S0=1, S1=0 [Shift Right Mode] S1=0, S0=1

53. S0=0, S1=1 [Shift Left Mode] S1=1, S0=0

54. S0=1, S1=1 [Parallel Load Mode] S1=1, S0=1

55. Counter Section 6.3

56. Types of Counter Binary Ripple Counter Synchronous Counter

57. Reset Binary Ripple Counter Respond to negative edge of the clock

58. Reset Binary Ripple Counter 0 0 0 0 1 1 1 1 1.D 0 (n+1)=A 0 (n) ’ The first flip-flop always toggles itself. 1 2 3 4 A3A2A1A0 0000 Each D flip-flop is designed to flip Itself. Each D flip-flop is triggered by the output of the previous DFF.

59. Reset Binary Ripple Counter 0→1 0 →0 1 →0 1 1 →1 1 2 3 4 A3A2A1A0 0000 0001

60. Reset Binary Ripple Counter 0→1 → 0 0 →0 →1 0 →0 →0 1 →0 → 1 1 1 →1 →1 1 2 3 4 1→1 →0 A3A2A1A0 0000 0001 0010

61. Reset Binary Ripple Counter Respond to negative edge of the clock 1 2 3 4 Each DFF is triggered by the previous DFF.

62. Counter as a Frequency Divider DecA3A2A1A0 00000 10001 20010 30011 40100 50101 60110 70111 81000 91001 101010 111011 121100 131101 141110 151111 140000 130001 120010 Start from 0, advance to 15, go back to 0. A 0 repeats after 2 cycles. A 1 repeats after 4 cycles. A 2 repeats after 8 cycles. A 3 repeats after 16 cycles. So a counter can be used as frequency divider. Reset is used to initialize the output to a 0

63. Synchronous Counters Synchronous counters are different from ripple counters in that clock pulses are applied to the input of all flip-flops.

64. Binary Counter 1 2 3 4 1 0 0 0 0 0 0 0

65. JK Flip-Flop

66. Binary Counter 1 2 3 4 1 0→1 0 →0 0→1 0 →0

67. 1 2 3 4 1 0→1 → 0 0 →0 →0 0→1 →0 0 →0 →1 0 →0 →0

68. Memory Section 7.2

69. Block Diagram of a Memory Unit

70. 74LS189 RAM [A3,A2,A1,A0]=address inputs [D3,D2,D1,D0]=data inputs [S3,S2,S1,S0]=outputs ME,WE control the direction of transfer VCC=power GND=ground

71. Logic Diagram memory cell Each word is enabled by the 4-input AND

72. Write →Read

73. Logic Diagram memory cell Each word is enabled by the 4-input AND

74. Switch Characteristics

75. Switching Time Waveforms 17 nS23 nS -7 nS for address -14 nS for data A negative hold time means that the address/data can change before the rising edge of WE because the there is internal delay through the chip.

76. Write (ME=0, WE=0) 0 0 1 0 1 1 1 1 D1 D2 D3 D4 [hi Z ? ]

77. READ (ME=0, WE=1) 1 0 0 1 Complement of data stored

78. HOLD (ME=1, WE=X) X 1 0 Hi-Z output