1. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 1 Chapter 3 Materials and Basic processes

2. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 2 Materials: Metals Right choice, right use and compatibility of materials is the key to good packaging and optimal properties. –Elemental metals: High electrical conductivity High thermal conductivity Higher thermal coefficient of expansion (TCE) than semiconductors and most ceramics –Alloys: taylored to many uses: Poorer electrical and thermal conductivity than elements Taylored TCE Lower melting point

3. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 3 Metals, continued (Table 3.1)

4. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 4 Alloys Alloys have poorer conductivity, both electrical and thermal. Fig. 3.1: Phase diagram for Sn/Pb. The eutectic mixture 63%/37% has a melting point of 183°C.

5. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 5 Insulators (Fig 3.1b)

6. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 6 Semiconductors, Si and GaAs High thermal conductivity Electrical conductivity spans many orders of magnitude, depending on doping Very low TCE "Machinable" by anisotropic etching (Si) Excellent protective oxide (Si)

7. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 7 Ceramics Inorganic, non-metallic Made by powder, compressing or tape casting, and high temperature treatment (600-1800 o C) Chemically and thermally very stable Electrical insulators Some ceramics are very good thermal conductors

8. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 8 Ceramics, continued

9. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 9 Ceramics, continued Dielectric loss: – tan  = (1/R)/  C = 1/Q –  =    (k´ - jk") – tan  = k"/k´. Main uses: –Substrates for hybrid circuits, component packages, SMD resistors –Multilayer capacitors –Future: Superconductors ?

10. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 10 Materials Fig 3.1.d

11. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 11 Ceramics, continued

12. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 12 Ceramics, continued

13. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 13 Glasses: Amorphous, supercooled liquids –Uses: Matrix for thick film pastes Hermetic seals Substrates, together with ceramics

14. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 14 PLASTICS Organic, synthetic polymer materials with numerous uses in electronics

15. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 15 Plastics, continued Composition, properties: –Monomers derived from benzene

16. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 16 Plastics, continued

17. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 17 Plastics, continued Requirements: –High electrical resistivity, high breakdown field, low dielectric losses, low dielectric constant –Thermal and mechanical stability –Thermal expansion compatible with Si and metals –High mechanical strength/softness and flexibility –Chemical resistance –Good adhesion to other materials –Ease of processing –Low water absorption, small changes of the properties during the effect of moisture.

18. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 18 Plastics, continued Composition, properties: –Linear, branched or crosslinked

19. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 19 Plastics, continued Thermoplastic or thermosetting

20. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 20 Plastics, continued Polymerization: A-, B-, C- stages. High electrical resistivity, low  r, low tan , high E crit Poor thermal conductors Visco-elastic Fig 3.7: The structural unit of certain monomers/polymers.

21. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 21 Plastics, continued –"Glass transition": change from glass-like to rubber - like

22. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 22 Plastic materials: Epoxy Phenolic Polyimide Teflon Polyester Silicone Polyurethane Parylene Acrylic Polysulphone, polyethersulphone, polyetherimide

23. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 23 Plastics, continued Fig. 3.9:a):The epoxide group, which is the building block in epoxy, b) - e): Starting materials for epoxy: b): Bisphenol A, which constitutes most of the starting material. The H- atoms in the places X are often replaced with Br to reduce the flammability; c): Epoxy novolac; d): The hardener dicyandiamide; e): The catalyst.

24. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 24 Plastics, continued

25. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 25 Basic processes

26. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 26 Photolithography Fig. 3.10:The steps in photolithographic transfer of patterns and the subsequent etching of metal films with negative photoresist. If positive resist is used, it is the illuminated part of the photoresist, which is removed during the development.

27. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 27 ScreenPrinting and Stencil Printing Fig. 3.11: Screen printing: a) and b): Printing process, c) and d): Details of the screen

28. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 28 Etching Wet, chemical etching "Dry" plasma- or reactive ion etching Examples, wet etching: Copper: FeCl 3 + Cu -> FeCl 2 + CuCl In addition: FeCl 3 + CuCl -> FeCl 2 + CuCl 2 Need organic etch resist, not good with PbSn. Gold: KI + I 2 -> KI 3 + KI (surplus) 3 KI 3 + 2 Au -> 2 KAuI 4 + KI

29. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 29 Plating Electrolytic plating: –Electric current of ions in electrolyte. External circuit needed. All separate parts of area to be plated must be electrically contacted to external circuit. Example: Cu in CuSO 4 /H 2 SO 4 Reaction at anode (Cu supply): Cu -> Cu 2+ + 2e - Reaction at catode (substrate): Cu 2+ + 2e - -> Cu

30. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 30 Plating, continued Chemical plating: –Takes place without external current –Needed when insulating surfacec are to be plated –Often preceeds electrolytic plating, to make all needed areas electrically conductive –Complex processes of "sensitizing", "activation" and plating

31. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 31 Vacuum deposition and sputtering Vacuum evaporation: –Chamber evacuated to less than 10 -6 Torr –Resistance heating –Metal evaporation

32. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 32 Other methods for deposition of conducting or insulating films DC Sputtering (Fig. 3.13.a)

33. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 33 Deposition, continued Radio Frequency AC Sputtering (Fig.3.13.b)

34. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 34 Methods for Electrical and Mechanical Contact Soldering –Wetting: (Fig. 3.14) Young´s eq.:  ls  l cos  s

35. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 35 Soldering, continued Most common solder alloy: 63 % Sn / 37 % Pb (eutectic) Melting point 183 o C

36. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 36 Soldering, continued –Fatigue: Coffin-Mansons formula: N 0.5 x  p = constant –Useful adition : 2 % Ag (Surface mount), to reduce leaching –Harmful contaminant: Au

37. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 37 Soldering, continued Fig.3.15:Behaviour of solder metal at different temperatures, schematically. [W. Engelmaier].

38. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 38 Soldering, continued Fig. 3.16: Solder joint fatigue in surface mounted assemblies is often caused by power cycling.

39. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 39 Soldering, continued Fig. 3.17: Experimental data for fatigue in Sn/Pb solder fillet by cyclical mechanical stress. High temperature and low cycling frequency gives the fastest failure, because the grain structure relaxes most and is damaged

40. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 40 Soldering, continued Fig. 3.18. a) Left: Dissolution rate of Ag in solder metal, and in solder metal with 2 % Ag, as function of temperature; b) Right: Dissolution rate of various metals in solder alloy

41. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 41 Soldering, continued

42. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 42 Soldering, continued Flux and cleaning –Purpose of flux: Dissolve and remove oxides etc. Protect surface Improve wetting –Categories: Soluble in organic liquids Water soluble –Types: Organic resin fluxes ("rosin") Organic non resin based fluxes Inorganic fluxes

43. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 43 Soldering: Flux and cleaning Fig. 3.19: Time for solder alloy to wet a pure Cu surface, depending on the activation of the solder flux. The degree of activation is given by the concentration of Cl - ions in the flux (temperature: 230 °C)

44. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 44 Soldering: Flux and cleaning –Designations: R (Rosin, non-activated): No clorine added. RMA (Rosin mildly activated): < 0.5 % Cl RA (Rosin, activated): > 0.5 % Cl –Cleaning –Freon (TCTFE) now forbidden. Replaced by alcohol etc. –Trend: No cleaning

45. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 45 Glueing Purposes: –Mechanical assembly –Electrical contact –Thermal contact Materials: polymers: –Epoxy, acrylic, phenolic, polyimide –Metal particles for electrical conductivity:  = 1 - 10 x 10 -6 ohm m –Metal or ceramic particles for thermal conductivity: K ≈ 1 - 3 W /m x o Ch

46. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 46 Glueing, continued Fig. 3.20: Thermal conductivity of epoxy adhesive with various amounts of Ag [3.16 a)]. The concentration is in volume % Ag. (23 vol. % corresponds to approximately 80 weight %).

47. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 47 Glueing, continued Fig. 3.21: The thermal resistance from the electronically active part, on top of the Si chip (¨junction¨) through a bonding layer of glue or soft solder and a thin alumina ceramic layer covered with Cu to heat sink. The samples with chips bonded by glueing, C and A, have approximately twice as high total thermal resistance as those which are soft soldered, D and B.

48. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 48 Chip Mounting: Die Bonding Fig. 3.22: Thermal resistance from junction to heat sink through adhesive of various thicknesses. For thick layers the resistance approaches the value calculated, based on the bulk thermal conductivity of the adhesive. For thin layers the resistance is higher, approaching a constant value, which indicates an "interface thermal resistance" caused by defects in the adhesive layer

49. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 49 Chip Mounting: Die Bonding, continued Eutectic die bonding: –Au/Si (363 o C), Au/Sn (280 o C) Soft soldering: Sn/Pb, Ag/Pb Glueing Adhesive cracking, fig. 3.23: Thermal cycling induces defects giving increased thermal resistance.

50. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 50 Chip Mounting: Die Bonding, continued Fig. 3.24: Use of adhesive for contacting IC-chips with small pitch, schematically: a): Anisotropic conductive adhesive, the conduction is through the metal particles in the adhesive; b): Electrically insulating adhesive, the conduction is through point contacts where the adhesive has been squeezed out.

51. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 51 Si Chip Electrical Contact Wire bonding Tape Automated Bonding (TAB) Flip chip Planar bonding

52. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 52 Wire Bonding Ultrasonic Thermo- compression Thermosonic Geometry Types –Ball - wedge: Shown in illustration –Wedge - wedge

53. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 53 Tape Automated Bonding (TAB) Standard process: –Fabrication of gold bumps (Fig. 3.28): Deposition of contact/barrier metals Photolithography Electroplating Strip and etch barrier metals

54. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 54 TAB, continued Fig. 3.26: A picture of a TAB film with the Cu pattern, as well as the holes in the film for excising the circuits, and the sprocket holes for moving the film during processing.

55. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 55 TAB, continued Fig. 3.27: The main steps in TAB processing.

56. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 56 Tape Automated Bonding (TAB) –Wafer cutting –Fabrication of TAB film Hole punching Cu foil lamination Lithography + etch of Cu pattern Tinning of Cu –Inner lead bonding (ILB)

57. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 57 TAB, continued –Protection (glob top) –Testing –Outer lead bonding: Excising, lead bending Placement/ther mode soldering

58. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 58 Advantages of TAB: High packaging density Can contact chips with >1000 I/O Excellent electrical properties (high frequency) Robust mounting Pre-testable (contrary to COB) Gold bumps give hermetic seal to chip Gang bonding gives high yield, is less time consuming than wirebonding TAB film can be used as daughter board

59. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 59 Disadvantages of TAB: Non-standard wafer processes Special custom design film for chip Needs special machine/tool for OLB Demanding repair Low availability of std. chips and TAB service Little standardization

60. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 60 Flip Chip Process: –Deposit barrier metals –Deposit solder bump metals (solder) by photolithography/metal mask and sputter or plating –Reflow –Cut wafer –Turn chip and mount on substrate –Heat substrate to reflow solder

61. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 61 Flip Chip, continued Advantages: –Highest packing density –Excellent hi freq. properties –Up to 10 000 I/O Disadvantages: –Very difficult placement and reliable solder/cleaning –Lack of thermal flexibility

62. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 62 Wire bonding, TAB and Flip Chip

63. Electronic Pack….. Chapter 3 Materials and Basic Processes Slide 63 Planar Bonding with Adaptive Routing Fig. 3.32: Planar bonding with laser-assisted adaptive conductor routing. The top two figures a) and b) show a substrate cross section with details of the mounting of the chip in an etched through-hole. Figure c) shows the conductor layers and polyimide insulation on top of the substrate. The bottom figures show an exploded view of all the layers.