1. Global Timing Constraints

2. Objectives After completing this module you will be able to… Apply global timing constraints to a simple synchronous design Use the Xilinx Constraints Editor to specify global timing constraints

3. The Effects of Timing Constraints  With global timing constraints  All timing paths are evaluated  I/O paths are improved (CLBs are place closer to I/O pins)  Without global timing constraints  Logic tends to be grouped to improve internal timing at the expense of I/O timing

4. Timing Constraints Define Your Performance Objectives Timing constraints define your timing objectives –Over-constraining gets you nothing, but costs extra PAR time –Always use timing constraints, even when your timing objective is modest Unrealistic timing constraints will cause the tools to stop –Your synthesis tool’s timing report and the Post-Map Static Timing Report contain performance estimates –Both will tell you if your constraints are realistic After implementing, review the Post-Place & Route Static Timing Report to determine if your objectives were met –If your constraints failed, use the Timing Report to determine the cause

5. Path Endpoints Path Endpoints are… –I/O pads –Synchronous elements FFs, Latches, Rams, DSP slices, SRLs, etc. Flip-FlopsLatches RAMs DSP48  Path Endpoints do NOT include… – LUTs – Nets, or any other asynchronous element

6. Creating Timing Constraints Step 1: Create groups of path endpoints Step 2: Specify a timing requirement between the groups  Creating timing constraints is a two step process  Global timing constraints use a default grouping of path endpoints which makes it easy to constrain your design

7. PERIOD Constraint Q FLOP1 D Q FLOP3 D BUFG CLK ADATA OUT2 OUT1 Q FLOP5 D Q FLOP4 D BUS [7..0] CDATA Q FLOP2 D  The PERIOD constraint covers paths between synchronous elements on a single clock domain – In this example, there is one clock signal (CLK) – There are five synchronous elements (all FFs) attach to the clock which means there are five path endpoints, in this case – There are three delay paths constrained between those five FFs

8. PERIOD Constraint The PERIOD constraint uses the most accurate timing information, so it considers… Clock skew between the source and destination flip-flops Synchronous elements clocked on the negative edge Unequal clock duty cycles Clock input jitter The Implementation tools use this information to place and route your design

9. Example of the PERIOD Constraint Assume… –50-percent duty cycle on CLK –PERIOD constraint of 10 ns –Because FF2 will be clocked on the falling edge of CLK, the path between the two flip-flops will be constrained to 50 percent of 10 ns = 5 ns –The implementation tools will automatically take into account that you are triggering one FF on the rising edge and another on the negative edge BUFG INV CLK FF1 FF2

10. Clock Input Jitter  The Xilinx Constraints Editor allows you to enter the input clock jitter  The Implementation tools will then use this information to manage the place and route solution found so the distributed clocks jitter can be tolerated

11. OFFSET IN/OUT Constraints = Combinatorial Logic CLK ADATA OUT2 OUT1 Q FLOP DQ D Q D Q D BUS [7..0] CDATA Q FLOP D BUFG OFFSET INOFFSET OUT  The Offset In constraint covers paths from input pads to synchronous elements  The Offset Out constraint covers paths from synchronous elements to output pads

12. OFFSET IN/OUT Constraints The Offset In/Out constraints takes the clock delay into account to report an effective input and output delay OFFSET IN = T_data_In - T_clk_In OFFSET OUT = T_data_Out + T_clk_Out Out Clk T_data _In T_data _Out T_clk _In OFFSET-OUT OFFSET-IN In T_clk _Out

13. OFFSET Constraints Reporting  Timing constraint reporting is handled by the Timing Analyzer  The Offset In/Out constraints take into account the clock delay and jitter

14. Apply Your Knowledge Which paths are constrained by a Period constraint on CLK1? –1 path is constrained, FF to Latch Which paths are constrained by a Period constraint on CLK2? –No paths are constrained, only 1 synchronous element

15. Launching the Constraints Editor Expand User Constraints in the Processes window Double-click Create Timing Constraints

16. Entering a PERIOD Constraint PERIOD constraints can be entered by clicking Clock Domains Constraints can be deleted by right-clicking the constraint Right-click here and select Create Constraint to make a PERIOD constraint

17. Multiple UCF Files Select which UCF to read constraints from and store constraints to Many designers keep their timing constraints in a separate UCF file –User Constraints File (user editable in many text editors) –Some designers like to keep their pin assignments, area constraints, and placement constraints in a separate UCF

18. PERIOD Constraint Options TIMESPEC name Specific constraint value –Active clock edge –Duty cycle Relative to other PERIOD TIMESPEC –Useful for designs with multiple clock signals –Can define both frequency and phase relationships Input jitter

19. Entering OFFSET Constraints Global OFFSET IN and OFFSET OUT constraints can be made from Inputs or Outputs Right-click here and select Create Constraint to make an OFFSET constraint

20. Apply Your Knowledge Given the system diagram below, what values would you put in the Constraints Editor so that the system will run at 100 MHz? –Assume no clock skew between devices 4 ns 5 ns Upstream Device Downstream Device

21. Answer Given the system diagram below, what values would you put in the Constraints Editor so that the system will run at 100 MHz? Answer: PERIOD = 10 ns, OFFSET IN = 6 ns, and OFFSET OUT = 5 ns 4 ns 5 ns 10 ns 6 ns 5 ns Upstream Device Downstream Device

22. Summary Performance expectations are communicated with timing constraints The PERIOD constraint covers delay paths between synchronous elements The OFFSET IN constraint covers delay paths from input pins to synchronous elements The OFFSET OUT constraint covers delay paths from synchronous elements to output pins Use the Constraints Editor to create timing constraints

23. Where Can I Learn More? Constraints Guide –Help  Software Manuals Entry strategies (UCF syntax and HDL syntax) Advanced timing constraints Timing Constraints User Guide –Help  Software Manuals  Timing Constraints User Guide Timing constraints (Global and Path Specific) Placement and Area constraints UCF syntax Xilinx Education Services courses –www.xilinx.com/training Path Specific Constraints are included with the Designing for Performance course Xilinx tools and architecture courses Basic FPGA architecture, Basic HDL Coding Techniques, and other topics

24. Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. © 2012 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. Trademark Information