1. Linac 4 LL RF Hardware Architecture and Design Status
Gregoire Hagmann, Jose Noirjean, Donat Stellfeld, Daniel Valuch, Julien Lollierou, Anirban Krishna Bhattacharyya, Philippe Baudrenghien
CERN-BE-RF-FB
John C. Molendijk CERN-BE-RF-CS
Reported by John C. Molendijk CERN-BE-RF-CS
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

2. J.C. Molendijk - Linac 4 Hardware Architecture and Design Status
Outline
Linac 4 LL RF hardware Architecture and Design Status
Hardware Architecture
Block Diagram
Chassis
Linac 4 Clocking Scheme
Cavity Loops Module
Switch & Limit Module
Tuner Loop Module
Conditioning DDS
Status of Electronic Designs
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

3. Linac 4 LL RF Block Diagram
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

4. J.C. Molendijk - Linac 4 Hardware Architecture and Design Status
Linac 4 LL RF Chassis
Private backplane (Based on LHC LL RF system)
Low noise Analog power supplies.
Fully buffered, Quad low-jitter differential clock distribution.
Hardware Timing distribution for chopping information etc.
Serial distribution of Reference RF phase.
220 mm deep slots offering sufficient real-estate for RF circuitry.
Geographical VME addressing.
Crate-wide JTAG enabling remote FPGA flashing through the crate manager module.
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

5. J.C. Molendijk - Linac 4 Hardware Architecture and Design Status
Linac 4 LL RF Chassis
Occupation
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

6. J.C. Molendijk - Linac 4 Hardware Architecture and Design Status
Linac 4 LL RF Chassis
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

7. J.C. Molendijk - Linac 4 Hardware Architecture and Design Status
Linac 4 Clocking Scheme
A RF reference-line will propagate the 352 MHz reference RF all along Linac4
At each cavity a directional coupler will extract some of the reference RF from the reference-line.
The antenna signals are routed in a bundle with the reference RF towards the cavity controller crate. All signals are submitted to similar drift effects.
At the cavity controller the reference RF is used to normalize the Antenna RF signal phase making these acquisitions robust against phase drift incurred by the cabling.
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

8. J.C. Molendijk - Linac 4 Hardware Architecture and Design Status
Linac 4 Clocking Scheme
Clocks Required for RF LL
Reference RF.
Local Oscillator (LO) for the mixers (Receivers and Modulators).
ADC clock (4 * fIF).
ADC clock /2 and ADC clock /4 for IQ demodulation.
10 MHz reference clock.
Critical Clocks
Reference RF, LO and ADC clock must have very low phase noise (jitter) to minimize demodulation errors and to maintain the effective number of bits (ENOB) in the Digital RF Receivers.
IQ Sampling & ADC Offset Compensation
TADClk
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

9. J.C. Molendijk - Linac 4 Hardware Architecture and Design Status
Linac 4 Clocking Scheme
LHC case
The beam synchronous RF is generated in SR4 (surface building) and then optically transported to the UX45 (cavern) faraday cages.
All RF synchronous clocks are there derived from the SR4 reference by one central clock Generator per beam.
A distribution system supplies the reference RF and all generated clocks (380, 80, 40 and 20 MHz) to all 8 cavity controllers crates per beam.
Linac 4
Reference RF is generated from a high quality Oscillator which is then amplified (~100W) to drive the Linac 4 RF reference line.
All RF synchronous clocks are derived and distributed within each cavity controller. Big savings in distribution and improved clock signal quality.
The Locally generated and distributed LO does not have to be phase drift stabilized since both the down and up convertors use the same (see p13).
The cavity controller’s Clock Generator Distributors receive and demodulate the Reference RF. The measured phase is distributed serially over the backplane to allow all modules to normalize their acquisitions. No need for individual ref. RF receivers per module.
Only the absolute 10 MHz reference is distributed individually.
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

10. J.C. Molendijk - Linac 4 Hardware Architecture and Design Status
Linac 4 Clocking Scheme
Clock Generator Distributor per Cavity Controller
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

11. J.C. Molendijk - Linac 4 Hardware Architecture and Design Status
Linac 4 Clocking Scheme
Phase Discriminator
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

12. J.C. Molendijk - Linac 4 Hardware Architecture and Design Status
Linac 4 Clocking Scheme
New Low noise LO PLL and distribution
ADF4106
R =16
N =15
Using std VCO
Using Coaxial resonator based VCO
LO L4 Jitter = 270 fs, Band integrated [10Hz-10MHz]
LO LHC Jitter=264 fs
Retained solution
LO L Jitter= 120 fs
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status
Designer J. Lollierou

13. J.C. Molendijk - Linac 4 Hardware Architecture and Design Status
Cavity Loops Module
Implements:
RF Feedback,
Adaptive FF and
Klystron Polar Loop
System Independent of LO phase
IQ Demodulators synchronized by Fc (use same demux signals as Ref-line demodulator).
De-serialized Reference-line RF Phase used to normalize the phase of the RF Measurements.
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

14. J.C. Molendijk - Linac 4 Hardware Architecture and Design Status
Linac 4 Switch and Limit
Block Diagram
Avoids overdriving the Klystron
Pin
Pdrive
Designer G. Hagmann
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

15. Linac 4 Tuner Loop Front-end
Simplified Block Diagram
Designer J. Noirjean
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

16. Linac 4 Tuner Loop Front-end
Designer J. Noirjean
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

17. Linac 4 Tuner Loop Module
Common for all Linac4 structures: DSP or
Software customized,
L. Arnaudon
Simplified Block Diagram
E_IcFwd = Vcav X IcFwd
VME register
Optimal Vcav Phase
Designer J. Noirjean
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

18. Linac 4 Conditioning DDS
Prototype to be tested on DTL prototype, end 2010
Simplified Block Diagram
DDS IF ~48 MHz
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

19. Status of Electronic Designs
Modules
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

20. Thank you for your attention.
J.C. Molendijk - Linac 4 Hardware Architecture and Design Status