1. A Fast-Locked All-Digital Phase-Locked Loop for Dynamic Frequency Scaling
Dian Huang
Ying Qiao

2. Motivation CMOS IC technology keeps further scaling
SoC benefits from All-Digital PLL (ADPLL) designs
Dynamic frequency scaling in CPU
Fast-locked phase-locked loop (PLL) for clock generation
Tradeoffs between locking time and clock jitter
We will focus on
ADPLL design with bang-bang phase detector (BBPHD)
Digitally controlled oscillator (DCO) frequency-search using algorithms with Successive-Approximation Registers (SAR)

3. ADPLL Architecture Conventional vs. Proposed ADPLL Architecture
Conventional BBPHD ADPLL
Proposed BBPHD ADPLL with SAR

4. Design Considerations
Tradeoff exists between frequency phase locking time and output clock jitter performance
𝑡 𝑙𝑜𝑐𝑘 = 𝜋 2𝜋 𝑓 𝑟𝑒𝑓 × 𝛽 𝑘 𝑣𝑐𝑜 − 𝑓 𝑜𝑓𝑓 𝑓 𝑟𝑒𝑓
𝑓 𝑟𝑒𝑓 – reference clock frequency
𝑓 𝑜𝑓𝑓 – initial frequency error
𝛽 𝑘 𝑣𝑐𝑜 – system loop gain
𝑞= 𝛽− 𝛼 1+2𝐷 2
β - Proportional path gain
α – Integral path gain
Δ𝑡 𝑝𝑝 = 𝑁 𝑘 𝑣𝑐𝑜 4 𝑞 𝐷 4 𝛼 𝐷 3 𝛼 2 𝑞+8 1+𝐷 2 𝛼 𝑞 𝐷 𝑞 3

5. Fast-locking Techniques
Simultaneous frequency and phase locking
Yang, JSSC ’10 – adaptive loop gain
Hung, Trans Circuit & Syst. ’11 – modified bang-bang algorithm
Detangled frequency and phase locking
Chung, JSSC ’11 – BSA frequency search + TDC phase locking

6. Proposed ADPLL Architecture

7. SAR-based Frequency Search
Reference clock
Divider output
Oscillator output
BBPHD UP signal

8. SAR-based Delay Search
Falling edge of divider output does not align with that of reference clock due to delay.
Add extra delay to reference clock
Once frequency search is done, CPU designer can choose whether input clock of PLL is reference clock or its delay version based on jitter and locking requirement.

9. Locking Procedure
2 cycles delay-search, 10 cycles frequency-search for a 10 bit DCO.
Remained frequency error and phase error are tiny.
Locks at 790ns

10. Five Stage DCO
DCO consists of 960 tri-state buffer: 64 row with each row has 15 buffers.
Five extra tri-state buffer are used to drive each to node to either Vdd or ground during reset for fast start-up
DCO Frequency Range: 0.42GHz ~ 12GHz

11. PI Controller
With proposed frequency-search algorithm, small 𝛃 and 𝛂 can be chosen.
𝛃 needs to be several time larger than 𝛂 for stability, but want 𝛃 to be 1 or 2 to minimize the quantization noise.
Integral path code increment by 1 only when it can increment by 4

12. Performance
Key Parameter
Technology
45nm
Locking Time
790ns
Jitter RMS
1.32ps
Jitter peak-to-peak
4.56ps
Power
Achieves 790ns locking time while maintaining 1.32ps rms jitter.
Peak-to-peak jitter is too optimistic.

13. Comparison [10] Hsu [8] Kim [9] Chung [2] Tierno This Work
[10] Hsu
[8] Kim
[9] Chung
[2] Tierno
This Work
CMOS Process
0.18µm
0.13µm
65nm
45nm
Core Area
0.14 mm2
0.2 mm2
0.07mm2
0.07 mm2
N/A
Power NA
Output Range
62~616MHz
0.3~1.4GHz
90~527MHz
0.8~12GHz
0.42~12GHz
Locking Time
3.5µs
*46 µs
790ns
Jitter RMS
Jitter peak-to-peak
1.35GHz

14. Conclusion
Proposed ADPLL realizes fast-locking without sacrificing jitter performance.
790ns locking time demonstrates that it is suitable to dynamic frequency scaling.
Future work includes ADPLL with smooth frequency change so that CPU does not needs to stall its instructions.