1. Methods for checking simulation correctness How do you know if your testcase passed or failed?

2. 3 checking methods n Predict and check n Check as you go n Trace and check later

3. Predict and check n How does it work? è Create the stimulus è Run the stimulus against an independent reference model è Save the predicted results è Run the stimulus on the simulation model è Compare the simulation results against the predicted results n Where is it used? è Processor verification è Chip verification

4. Predict and check - cont'd... m 00000100 830445cd6673da21 m 00000108 34539877c7c82243 m 00000110 cd565479802ad999... i ld r4, (100) i ld r8, (110) i add r4, r8, r3 i add r3, r4, r8 i add r3, r3, r8... m 00000100 830445cd98098001 m 00000108 34539877c7c82243...

5. Predict and check - cont'd n Does not require run time interaction with the model n Reference model tends to be highly reusable n Quickly up and running and producing bugs n Bugs must propagate to a result n Bugs can be overwritten n Cascade affect can make it difficult to isolate the source of the problem n Results have to be predictable from the testcase alone n Input may have to be restricted to guarantee predictable results Advantages Disadvantages

6. Check as you go n How does it work? è Create an environment to stimulate, observe and predict the behavior of the simulation model è As the simulation is running the environment should compare the expected behavior to the observed behavior è Stop the testcase when the expected and observed behavior is different n Where is it used? è unit verification è chip verification è subsystem verification

7. DUV Driver A Driver B Driver C IM A IM B IM C Check as you go - cont'd Unit monitor Global transaction monitor ("Scoreboard") (IM = Interface Monitor)

8. Check as you go - cont'd n Highly effective at finding all types of bugs n Stops the test as soon as the error is detected n Error messages can be very specific and are usually directly related to the problem n Environment can choose what to do next based upon observed events n Environment code is greater than the VHDL n Environment may be created to match the implementation instead of the design intent n Takes time to make the environment effective n Requires run time iteraction with the model n Code is very design specific and not reusable Advantages Disadvantages

9. Trace and check later n How does it work? è Tracers are created to observe and record the activity of specific interfaces è During the simulation of the testcase the trace information is gathered and saved è After the simulation is complete, the tracers are analyzed for any rule violations n Where is it used? è system verification è protocol verification

10. Trace and check later - cont'd Memory Controller I/O Hub L2 Cache L1 Cache Core L2 Cache L1 Cache Core System Bus I/O Behavior I/O Bus

11. Trace and check later - cont'd n Don't spend simulation time checking results n Stimulus generation is not constrained n Allows correlation between distant parts of the design under verification n Tracers and checkers reusable for standard interfaces n Bugs must propagate to an observed interface to be seen n Testcase will run to completion before any error checking is started (wasted cycles) n Requires run time interaction with the model Advantages Disadvantages

12. P1 P2 P3 P4P5 P6 Switch Data Response Timeout Node Switch Memory Controller Other Nodes I/O Read addr 100 Respond Shared