1. FPGA Implementation of a Message-Passing OFDM Receiver for Impulsive Noise Channels Prof. Brian L. Evans, Wireless Networking and Communications Group, The University of Texas at Austin Students: Mr. Karl Nieman, Mr. Marcel Nassar and Ms. Jing Lin Approximate Message Passing (AMP) OFDM Objective: Implement a real-time OFDM receiver with impulsive noise mitigation for use in power line communications (PLC). AMP PLC Test System Powered by NI Products Impulsive Noise in PLC OFDM transmits data over multiple independent subcarriers (tones) FFT spreads out impulsive noise across all subcarriers IFFTFilter ++ FFT Equalizer and detector Impulsive noise estimation Gaussian (w) + Impulsive Noise (e) Vector of symbol amplitudes (complex) + - Channel Receiver x y Conventional OFDM system Added in our system Project supported by NI, Freescale, IBM, and TI DSP Design Diagram (step 2 of algorithm) Outdoor medium-voltage line (St. Louis, MO) Cyclostationary noise becomes impulsive after interleaving Interleave Indoor low-voltage line (UT Campus) Local utility MV-LV transformer Data concentrator Smart meters Iterative algorithm (4 iterations used) In-band noise inferred from out-of-band guard tones LabVIEW DSP Design Module (a high-level graphical synthesis tool) was used to map processing to FPGA Mapped to fixed-point using MATLAB toolbox RT controller LabVIEW RT data symbol generation FlexRIO FPGA Module 1 (G3TX) LabVIEW DSP Design Module data and reference symbol interleave reference symbol LUT 43.2 kSps 8.6 kSps zero padding (null tones) generate complex conjugate pair 103.6 kSps 256 IFFT w/ 22 CP insertion 368.3 kSps NI 5781 16-bit DAC 10 MSps RT controller LabVIEW RT BER/SNR calculation w/ and w/o AMP FlexRIO FPGA Module 2 (G3RX) LabVIEW DSP Design Module NI 5781 14-bit ADC sample rate conversion 10 MSps400 kSps time and frequency offset correction 400 kSps 256 FFT w/ 22 CP removal, noise injection 368.3 kSps FlexRIO FPGA Module 3 (AMPEQ) LabVIEW DSP Design Module null tone and active tone separation 184.2 kSps 51.8 kSps channel estimation/ ZF equalization AMP noise estimate Subtract noise estimate from active tones data and reference symbol de- interleave 51.8 kSps 8.6 kSps Host Computer LabVIEW 43.1 kSps sample rate conversion 400 kSps 51.8 kSps 256 FFT, tone select 51.8 kSps 368.3 kSps testbench control/data visualization differential MCX pair TX Chassis RX Chassis 1 × PXIe-1082 1 × PXIe-8133 1 × PXIe-7965R 1 × NI-5781 FAM differential MCX pair (quadrature component = 0) 1 × PXIe-1082 1 × PXIe-8133 2 × PXIe-7965R 1 × NI-5781 FAM LabVIEW Front Panel BER Results UtilizationTXRXAMP+EQ FPGA123 total slices32.6%64.0%94.2% slice reg.15.8%39.3%59.0% slice LUTs17.6%42.4%71.4% DSP48s2.0%7.3%27.3% blockRAMs7.8%18.4%29.1% FPGA Resource Usage BER analyzed over typical PLC operating range Up to 8 dB SNR recovered using AMP algorithm Communication in a Smart Grid with AMP conventionalinput impulsive noise Project website: http://users.ece.utexas.edu/~bevans/projects/plc/