Download presentation
Presentation is loading. Please wait.
1
ECE2030 Introduction to Computer Engineering Lecture 15: Registers, Toggle Cells, Counters Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech
2
2 4-bit Register Register is the most fundamental storage, e.g. –x86 ISA has 8 general purpose registers –MIPS ISA has 32 general purpose registers Each 1-bit Flip-flop is a single bit register Cascade 4 of 1-bit FFs = A 4-bit Register in0 1-bit D Flip Flop 1111 out0 2222 in1 1-bit D Flip Flop out1 in2 1-bit D Flip Flop out2 in3 1-bit D Flip Flop out3
3
3 Read/Write Control a Register Read: Retrieve data stored inside a flip-flop Write: Update with a new input data into a flip-flop Given 1 and 2 are continuous clock signals Output 1-bit D Flip Flop 1111 2222 In READ mode Output 1-bit D Flip Flop 1111 2222Input In Write mode
4
4 Read/Write Control a Register Output 1-bit D Flip Flop 1111 2222 Input R/W
5
5 Another Read/Write Control of a Register Output 1-bit D Flip Flop 1111 2222 Input R/W Clock Gating
6
6 4-bit Register with Parallel Load Q3 11 22 DQ D3 R / W Q2 11 22 DQ D2 Q1 11 22 DQ D1 Q0 11 22 DQ D0
7
7 Logical Shift Register 11 22 DQ 11 22 DQ 11 22 DQ 11 22 DQ A3 A2A1A0 11 22 11 22 11 22 11 22 Right Shift
8
8 Arithmetic Shift Register 11 22 DQ 11 22 DQ 11 22 DQ 11 22 DQ A3 A2A1A0 11 22 11 22 11 22 11 22 Right Shift
9
9 Bidirectional Shift Register with Load (1-bit shown) 4-to-1 Mux 11 100100 s1 s0 11 22 DQ 11 22 DQ 11 22 DQ Q i+1 Q i Q i-1 DiDi 00: No shift 01: Shift Left 10: Shift Right 11: Load from Di
10
10 Serial Transfer DQ DQ DQDQ Shift Out (SO) Shift In (SI) Clock
11
11 Serial Shift Register DQ DQ DQDQ Shift Out (SO) (SI) Clock Clear SR4 SI SO Clock Clear
12
12 Design a Serial Adder (yet another adder) SR4 A SI SO Clock Clear SR4 B SI SO Clock Clear + A B S Co Ci DQ Clear A A+B (1)Clear SRs (2)B 0111 (4 clks) (3)B=0111 A=0000 (4)B=1011 A=1000 (5)B=1101 A=1100 (6)B=0110 A=1110 (7)B=0011 A=0111 (8)B=0001 A=0011 (9)B=0000 A=1001 (10)B=0000 A=0100 (11)B=0000 A=1010 Ex: 0111 (A) + 0011 (B) ---------------- Input
13
13 Toggle Flip-Flop (Toggle Cell) Upon every clock, the output result is toggled D1Q1D2Q2 D1 D1 Q1=D2 Q2 En En En Transparent latch Transparent latch
14
14 Toggle Flip-Flop D1Q1D2Q2 1111 2222 Toggle Enable Bit (or TE bit) Toggle bit controls to toggle (T=1) or not to toggle (T=0) Transparent latch Transparent latch
15
15 Toggle F/F with Clear bit ClearToggle Enable Present Output Next Output 0XX0 1000 1011 1101 1110 D1Q1D2Q2 1111 2222 TE Bit Output Clear Transparent latch Transparent latch Note that output changes every clock cycle (e.g. rising edge or falling edge)
16
16 Toggle F/F Symbol TE Q CLR 1111 2222 ClearTEPresent QNext Q 0XX0 1000 1011 1101 1110
17
17 Counters A register counts up or down per clock period –Count in binary –Could be preset: (with parallel loads) Types of counters –Ripple counter –Synchronous counter –Mod-n counter –Up/down counter –BCD counter –Gray code counter –Ring counter a 1 moves in a ring from one F/F to the next –Johnson counter (or twisted ring count.) The MSB is inversed and passed to the LSB)
18
18 2-bit Ripple Counter TE Q CLR 1111 2222 TE Q CLR O0 O1 Count Enable 1111 O0
19
19 2-bit Ripple Counter TE Q CLR 1111 2222 TE Q CLR O0 O1 Count Enable 1111 O0 O1 0000 1010 0101 1111 0000 1010 0101
20
20 4-bit Ripple Counter Count Enable 1111 O0 O1 TE Q CLR 1111 2222 TE Q CLR O0 O1 TE Q CLR O2 TE Q CLR O3 O2 O3
21
21 4-bit Synchronous Counter Count Enable TE Q CLR 1111 2222 O0 TE Q CLR O1 TE Q CLR O2 TE Q CLR O3 Clocks are applied to the inputs of all the F/F 1111 O0=TE1O1 O2 O4
22
22 Modulo-N (or Divide-by-N) Counter Mod-N –Count from 0 to N-1 –Then reset and start over CLR CE O3O2O1O0 1111 2222 4-bit Counter MOD-10 counter (a BCD Counter) CLR Terminal Count (TC)
23
23 Cascaded BCD Counter CLR CE O3O2O1O0 1111 2222 Mod-10Counter TC CLR CE O3O2O1O0 1111 2222 Mod-10Counter TC O7O6O5O4O3O2O1O0 Vdd
Similar presentations
