1. Introduction to Microcontrollers
Application-Specific Integrated Circuits Michael John Sebastian Smith
Addison Wesley, 1997

2. Components of a Computer System
Memory
System
Input/Output
System
CPU

3. Microcontrollers Microcontoller Chip
Microcontrollers integrate all the components of a computer system onto a single chip
All components are optimized to perform the functions necessary to control a larger system
Size, capability, cost, and power consumption are more important considerations
8 bit microcontrollers have the majority of the market right now, but 16 and 32 bit microcontrollers are available and gaining market share
ROM
Memory
RAM
Memory
Microcontoller
Chip
CPU
Core
System
I/O

4. Microcontroller Components
CPU
May be an adaptation of an existing microprocessor or a completely new architecture
Instruction set is typically modified to deal with new I/O system
Memory
On-chip NVRM to hold program - can be mask programmable ROM, OTP ROM, or EPROM/EEPROM
On-chip RAM for variable storage - usually small amount and can double as mP’s registers
Both can be expanded using off-chip memory (extended microcontroller mode)

5. Microcontroller Components (cont.)
I/O system - tailored to provide services usually required in embedded control applications
Binary I/O pins (buffered, built-in pull ups, etc.)
Timers/Counters
Pulse Width Modulation (PWM) outputs
Capture inputs
AD and DA converters
UART or other communication controllers
Miscellaneous
Oscillator options
Reset options
Sleep/reduced power modes
External interrupts
Watchdog timers

6. Microcontroller Binary I/O pins
Binary I/O pins are pins that can either write (output) a ‘1’ (Vdd) or ‘0’ (Gnd) value, or read (input) a ‘1’ or ‘0’ value
Direction (input or output) is typically set on a per bit basis with a direction bit
These type of I/Os are often multiplexed with other I/O functions
Pull up (or pull down) resistors are typically included for connection to a bus
Drive capability is usually in the medium range (20 mA - 60 mA)
Interrupt on change features are sometimes included

7. Microcontroller Counter/Timers
Timers are special registers within the microcontroller that are configured as binary counters
Timer registers can be preloaded with a starting value and possibly have an ending value (other than overflow) specified
Overflow or hitting the end value generates an interrupt to the processor
Timer register clocking:
Internal CPU clock - timer mode
External clock via a dedicated I/O pin - counter mode
Timers are the basis for PWM outputs and Capture inputs
Timers are also sometimes used by the external communications functions (UARTS, etc.)

8. Microcontroller PWM Outputs
Pulse Width Modulation (PWM) outputs are special purpose outputs that can generate a specified train of pulses
Internal general purpose timer registers are often used to generate the pulse train
When generating a PWM output, timers can not be used for other purposes
Typically the period and duty cycle of the pulse train are specified
Period is specified in counting units of the specified timer
Duty cycle is specified as the actual width (in timer units) of the “on” pulse
Period
Duty
Cycle

9. Microcontroller Capture Inputs
Capture inputs are used to count external events
A general purpose timer is associated with each capture register
The timer is incremented each time the external event occurs
The external event can be a rising or falling edge on the capture input, or multiples there of (i.e., every 4th rising/falling edge, every 16th rising/falling edge)
The capture (timer) register value can be read or an interrupt can be generated when it equals a specified value

10. Other Microcontroller I/O functions
Some microcontrollers include an internal Analog-to-Digital converter (some with multiple channels)
Conversion values are placed in a special purpose register
Conversion is started under software control
Accuracy (no. of bits) is variable, but is typically in the 8-16 bit range
Input voltage usually in the range of 0 to 2X or 3X Vdd
Digital-to-Analog converters are also sometimes provided
Input is typically one or two processor data words wide
Output is 0 to 2X or 3X Vdd
Current drive is equivalent to other I/O ports

11. Other Microcontroller I/O functions (etc.)
Most microcontrollers include built-in serial communications capabilities
Universal Asynchronous Receiver/Transmitter (UART)
Serial Peripheral Interface (SPIâ)
Microwireâ
I2C
Most microcontrollers also include the following capabilities for dealing with real-time systems:
Optional oscillator sources such as external clock, external crystal, or simple RC timing circuit
Watchdog timers that will interrupt the CPU after a certain period of time if the CPU does not reset it - useful for recovering from software malfunctions
Power-down or sleep modes from which wake-up occurs on interrupts (from watchdog timer, timer/counters, capture inputs, external interrupts, etc.)
SPI - Motorola’s serial interface standard. May be bi-directional or one-way
Microwire - National’s master-slave communications mechanism
I2C - Philips’ serial bus initially developed for communication between components in digital TV sets

12. Microchip PIC17C4X Series Microcontrollers
Harvard architecture - 16 bit instructions, 8 bit data
RISC instruction set - 58 total instructions
Single cycle (4 clock cycles) instruction execution except for program branches and table operation which require 2 cycles
DC (0Hz) to 33 MHz clock input - DC to 121ns instruction cycle time
Hardware multiplier (except PIC17C42
40 pin DIP package
EPROM 2K, 4K, and 8K X 16 options
External program memory up to 64K X 16 can be used (requires the elimination of 16 I/O pins)
UV EPROM
OTP
Manufacturer Programmed
Data RAM 232 or 454 bytes available

13. Microchip PIC17C4X Series Microcontrollers (cont.)
33 I/O pins with individual direction control
Two capture inputs and two PWM outputs
Two 16 bit and two 8 bit timers
Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
SPI
Microwire
I2C
Power-on Reset, Power-up and Oscillator Start-up Timers
Watchdog timer
Sleep mode
Selectable oscillator options

14. PIC17C4X Pinout

15. PIC17C4X I/O Functions

16. PIC17C4X I/O Functions (cont.)

17. PIC17C4X I/O Functions (cont.)

18. PIC17C4X Architecture

19. PIC17C4X Instruction Timing

20. PIC17C4X Instruction Formats

21. PIC17C4X Opcode Fields

22. PIC17C4X Instructions

23. PIC17C4X Instructions (cont.)

24. PIC17C4X Memory Organization

25. PIC17C4X Memory Modes 4 available modes of operation:
Microprocessor
Microcontroller
Extended Microcontroller
Protected Microcontroller
Microcontroller and protected microcontoller modes only allow internal execution
Protected microcontroller model also enables code protection feature
Extended microcontroller mode accesses both internal and external program memory
Microprocessor mode only accesses external program memory

26. Interfacing the PIC17C4X to External Program Memory

27. Interfacing the PIC17C4X to External Program Memory (cont.)

28. PIC17C4X Register File (Data Memory) Map

29. PIC17C4X Special Function Registers

30. PIC17C4X Special Function Registers (cont.)

31. PIC17C4X Interrupts
PIC17C4X microcontrollers can have 11 sources of interrupts:
External interrupt via RA0/INT pin
Change on RB7:RB0 pins
TMR0 Overflow
TMR1 Overflow
TMR2 Overflow
TMR3 Overflow
There are 4 interrupt vectors corresponding to these 4 interrupt sources:
T0CKI edge occurred
Any peripheral interrupt (i.e., everything else)
Individual interrupt flags for the first 3 are cleared when the interrupt vector is executed
USART Transmit buffer empty
USART Receive buffer full
Capture 1
Capture 2
T0CKI edge occurred

32. PIC17C4X Interrupts (cont.)
Peripheral interrupt flags are not automatically cleared to allow testing for which type of interrupt occurred
These flags must be cleared in software to avoid infinite interrupt loops
Only the PC is automatically saved on the stack when the interrupt occurs, all other registers used must be explicitly saved in the ISR
There are 4 registers used in control and status of interrupts:
CPUSTA
INTSTA
PIE
PIR
CPUSTA register contains the Global Interrupt Disable (GLINTD) bit
When GLINTD is set, interrupts are disabled
GLINTD is automatically set whenever an interrupt is responded to

33. PIC17C4X Interrupt Logic

34. PIC17C4X Interrupt Status Register (INSTA)
The INSTA contains the individual flag (interrupt request) bits and the individual interrupt enable bits for the four major types of interrupts
If a peripheral interrupt occurred, the PIR register must be examined to determine the requesting peripheral

35. PIC17C4X Peripheral Interrupt Enable Register (PIE)
The PIE register contains the individual interrupt enable bits for the peripherals

36. PIC17C4X Peripheral Interrupt Request Register (PIR)
The PIR register contains the individual flag (interrupt request) bits for the peripherals

37. PIC17C4X I/O Ports
PIC17C4X micrcontollers have five I/O ports - PORTA through PORTE
PORTB through PORTE have a corresponding Data Direction Register (DDRX) to configure pins as either inputs or outputs
PORTC, PORTD, and PORTE pins are multiplexed with the system bus - these ports are not available in the microprocessor or extended microcontroller modes
PORTA and PORTB are multiplexed with the peripheral features of the microcontroller
Timer modules
Capture module
PWM module
USART module
External interrupt pins
The PWM and USART modules automatically configure their I/O pins - the other modules must have their DDR bits configured appropriately

38. PIC17C4X PORTA PORTA does not have a DDR
RA0/INT is either a data input or external interrupt input
RA1/T0CKI is either a data input, the TMR0 external clock, or an external interrupt input
RA2, RA3 are open drain outputs - simply write to PORTA register to output values to them, the other PORTA pins are unaffected
RA4, RA5 are either inputs or USART pins - they are automatically configured by the USART module if it is active
Bit 7 of the PORTA register controls the weak pull-up resistors for PORTB

39. PIC17C4X PORTA (cont.)

40. PIC17C4X PORTB PORTB is an 8-bit wide bi-directional port
The corresponding data direction register is DDRB
A ‘1’ in the bit of DDRB configures the pin as an input
A ‘0’ in the bit of DDRB configures the pin as an output
Reading PORTB reads the status of the pins - writing PORTB writes to the port latch
Each pin of PORTB has a weak internal pull-up resistor enabled by clearing RBPU
The weak pull-ups are enabled on reset and automatically turned off when a pin is configured as an output
PORTB has an interrupt on change feature
Only pins configured as inputs cause this interrupt to occur
Input values are compared with the value in the PORTB data latch - any mismatch causes the interrupt
This interrupt can wake the processor from the SLEEP mode

41. PIC17C4X PORTB (cont.)

42. PIC17C4X PORTC PORTC is an 8-bit wide bi-directional port
The corresponding data direction register is DDRC
A ‘1’ in the bit of DDRC configures the pin as an input
A ‘0’ in the bit of DDRC configures the pin as an output
Reading PORTC reads the status of the pins - writing PORTC writes to the port latch
In the microprocessor or extended microcontroller mode, this port is the low order byte of the system bus (AD7:AD0) and is unavailable as an I/O port

43. PIC17C4X PORTC (cont.)

44. PIC17C4X PORTD PORTD is an 8-bit wide bi-directional port
The corresponding data direction register is DDRD
A ‘1’ in the bit of DDRD configures the pin as an input
A ‘0’ in the bit of DDRD configures the pin as an output
Reading PORTD reads the status of the pins - writing PORTD writes to the port latch
In the microprocessor or extended microcontroller mode, this port is the high order byte of the system bus (AD15:AD8) and is unavailable as an I/O port

45. PIC17C4X PORTD (cont.)

46. PIC17C4X PORTE PORTE is an 3-bit wide bi-directional port
The corresponding data direction register is DDRE
A ‘1’ in the bit of DDRE configures the pin as an input
A ‘0’ in the bit of DDRE configures the pin as an output
Reading PORTE reads the status of the pins - writing PORTE writes to the port latch
In the microprocessor or extended microcontroller mode, this port contains the control bits for the system bus (Address Latch Enable ALE, Output Enable OE, and Write WR) and is unavailable as an I/O port

47. PIC17C4X PORTE (cont.)

48. PIC17C4X Timer Resources
The PIC17C4x microcontroller has four timer modules
Timer bit timer with programmable 8-bit prescaler
Timer1 - 8-bit timer
Timer2 - 8-bit timer
Timer bit timer
Each timer module can generate an interrupt (although they are different types of interrupts for the different timers)
The Pulse Width Modulation (PWM) outputs use the TMR1 and TMR2 timers and the Capture inputs use the TMR3 timer

49. PIC17C4X Timer0 The Timer0 module contains a 16-bit timer/counter
The high byte of the timer is TMR0H and the low byte is TMR0L
The Timer0 module includes an 8-bit programmable prescaler that makes it an effective 24 bit overflow timer
The clock source is programmable to be either the internal instruction clock (timer) or the RA1/T0CKI pin (counter)
The external edge that the time increments on can be selected in software
When the timer rolls over from FFFFh to 0000h, the TMR0 Interrupt Flag bit (T0IF) is set and the processor vectors to the TMR0 interrupt vector - the T0IF bit is automatically cleared
The prescaler output (input to the timer) is synchronized with the internal clock
The timer high and low bytes can be written and read in software
Care must be taken to ensure that the value doesn’t roll over during the operation

50. PIC17C4X Timer0 (cont.)

51. PIC17C4X Timer0 (cont.)

52. PIC17C4X Timer1, Timer2, and Timer3
Timer1 and Timer2 are two 8-bit timer/counters (TMR1 and TMR2) with an associated period register (PR1 and PR2)
Both timers can either increment on the internal clock or on the falling edge of the external clock on pin RB4/TCKL12
Timer1 and Timer2 can also be configured to operate as a single 16-bit timer
Timer1 and Timer2 are the time base for the PWM outputs
Timer3 is a 16-bit timer/counter consisting of the TMR3H and TMR3L bytes
Timer3 can increment from the internal clock or the RB5/TCLK3 pin
Timer3 is the time base for the two 16 bit captures
Two registers (PR3H/CA1H:PR3L/CA1L) are used as a 16-bit period register or a 16-bit Capture1 register
Two registers (CA2H:CA2L) are strictly the Capture2 registers

53. PIC17C4X Timer1 and Timer2
Timer1 and Timer2 operate in 8-bit mode when the T16 bit is clear
Their clocks can be independently selected to be either internal or an external falling edge (RB4/TCLK12)
The timers increment from 00h until they equal the period register (PRx) and then reset in the next cycle
The timer interrupt flag (TMR1F and TMR2F flag is set when the timer rolls over (and their individual interrupts are enabled)
The Timer1 and Timer2 interrupts are peripheral interrupts
Peripheral interrupts as well as the individual timer interrupts must be enabled
The PIR register must be checked to determine the source of interrupts
The individual timer interrupt flags must be cleared in software
When the T16 bit is set Timer1 and Timer2 form a 16-bit timer/counter
The timer counts from 0000h until it equals the period register (PR2:PR1)
The TMR1CS bit controls the clock source for the 16-bit timer

54. PIC17C4X Timer1 and Timer2 (cont.)

55. PIC17C4X Timer1 and Timer2 (cont.)

56. PIC17C4X Timer1 and Timer2 (cont.)

57. PIC17C4X Timer1 and Timer2 (cont.)

58. PIC17C4X PWM Outputs
Two high-speed Pulse Width Modulation (PWM) outputs are provided (RB2/PWM1 and RB3/PWM2)
PWM1 uses Timer1 as its time-base while PWM2 can be configured to use either Timer1 or TImer2 as its time-base
Each PWM output has a maximum resolution of 10-bits (with the addition of 2-bit internal Q clock or 2 bits of the prescaler)
The PWM1ON and PWM2ON bits enable the PWM outputs and the corresponding DDRB bits are ignored
The PWM periods are determined by the PR1 and PR2 registers:
period of PWM1 = [(PR1) + 1] x 4Tosc
period of PWM2 = [(PR2) + 1] x 4Tosc

59. PIC17C4X PWM Outputs (cont.)
The duty cycle is determined by the 10-bit value DCx<9:0> where DCx<9:2>=PWxDCH<7:0> and DCx<1:0>=PWxDCL<7:6>
PWMx Duty Cycle = (DCx) x Tosc
If DCx=0 then the duty cycle is zero, if PRx=PWxDCH then the PWM output will be low for one to four Q-clocks depending on PWxDCL<7:6>
For a 100% duty cycle, PWxDCH must be greater than the PRx value
The Timer1 and Timer2 interrupts can be enabled when using them for a PWM time-base - allows the user to write a new duty cycle value before the timer roll-over
Using the external clock for the time-base of the PWM outputs can cause jitter in the duty cycle and period due to the synchronization with the internal Q clock

60. PIC17C4X PWM Outputs (cont.)

61. PIC17C4X PWM Outputs (cont.)

62. PIC17C4X Timer3
Timer3 is a 16-bit timer/counter consisting of the TMR3H and TMR3L bytes
When the TMR3CS bit is clear, the timer increments every instruction cycle - when it is clear, it increments every falling edge of the RB5/TCKL3 pin
The TMR3ON bit must be set of the timer to increment
Timer3 has two modes of operation depending on the CA1/PR3 bit:
One capture and one period register
Dual capture register mode
The 16-bit capture registers capture the value of Timer3 when events are detected on the capture pins (RB0/CAP1 and RB1/CAP2)
An event can be:
a rising edge
a falling edge
every 4th rising edge
every 16th rising edge

63. PIC17C4X One Capture and One Period Register Mode
This mode is selected if the CA1/PR3 bit is clear
The PR3H/CA1H and PR3L/CA1L registers form a 16-bit period register for Timer3 - Timer3 increments from 0000h to the value in the period register and then rolls over
The CA2ED1 and CA2ED0 bits determine the event on which capture will be made:
capture on every falling edge (00)
capture on every rising edge (01)
capture on every 4th rising edge (10)
capture on every 16th rising edge (11)
On a capture event, the value of TMR3H/TMR3L will be copied into the CA2H/CA2L register and the CA2IF interrupt bit is set (if enabled with CA2IE)
A capture overflow bit CA2OVF value of ‘1’ indicates that the value in the capture register had not been read before the next capture event occurred
The new value of TMR3 is not copied into the capture register and the overflow flag is not set until the value in the capture register is read

64. PIC17C4X One Capture and One Period Register Mode (cont.)

65. PIC17C4X Dual Capture Register Mode
This mode is selected if the CA1/PR3 bit is set
TMR3 runs without a period register and increments from 0000h to FFFFh and then rolls over - an interrupt (TMR3IF) can be generated on this roll over
The two 16-bit capture registers are PR3H/CA1H/PR3H/CA1L and CA2H/CA2L
Capture modes are separately configured by the CA1ED1, CA1ED0 and CA2ED1 and CA2ED0 bits
Interrupts are separately enabled (CA1IE and CA2IE) and flagged (CA1IF and CA2IF)
Likewise, overflow is separately indicated (CA1OVF and CA2OVF)

66. PIC17C4X Dual Capture Register Mode(cont.)

67. PIC17C4X Capture Inputs (cont.)

68. PIC17C4X Universal Synchronous Asynchronous Receiver Transmitter (USART)
USART is a serial I/O module that can be configured as a full duplex asynchronous system or a half duplex synchronous system
The USART has the following modes:
Asynchronous (full duplex)
Synchronous - Master (half duplex)
Synchronous - Slave (half duplex)
The USART can communicate using a number of different protocols:
RS232
SPI
Microwire
I2C

69. PIC17C4X USART

70. PIC17C4X USART (cont.)

71. PIC17C4X USART (cont.)

72. PIC17C4X USART (cont.)

73. PIC17C4X Special Features
Like all microcontrollers, the PIC17C4X includes several additional special features to deal with the needs of real-time embedded applications:
Oscillator type selection - RC oscillator saves system cost while the LF crystal option saves power
Various Reset utilities
Power-on Reset - processor automatically resets on power-up
Power-up timer - provides a fixed 96 ms delay on power-up to allow power supply to stabilize
Oscillator Start-up timer - keeps the chip in reset until the oscillator stabilizes
Interrupts
Watchdog Timer
Sleep mode - low current power-down mode, user can wake through external reset, watchdog timer reset or an interrupt
Code protection

74. PIC17C4X Oscillator Configurations

75. PIC17C4X Oscillator Configurations (cont.)

76. PIC17C4X Watchdog Timer
The Watchdog Timer’s (WDT) function is to recover from software malfunctions
Uses an internal free-running RC oscillator as its clock source
The WDT can only be turned off via EPROM bits
The WDT has a nominal time-out period of 12 ms - if longer time-outs are desired, a prescaler with a division ratio of up to 1:256 can be assigned to the WDT thus realizing time-out periods of up to 3 seconds
The CLRWDT and SLEEP instructions clear the WDT
A WDT time-out generates a reset condition
Software must check to see if the reset was due to a WDT time-out by checking the TO bit in the CPU status register

77. PIC17C4X Watchdog Timer

78. PIC17C4X Sleep (Power-down) Mode
Sleep mode is entered by executing a SLEEP instruction
In Sleep mode, the oscillator driver is turned off and the I/O ports maintain their driven value (high, low or high-impedance)
The microcontroller can wake from Sleep mode through one of the following events:
A Power-on Reset
External reset on the MCLR/Vpp pin
WDT Reset (if WDT was enabled)
Interrupt from RA0/INT pin, RB post change, T0CKI interrupt, or some peripheral interrupts
Capture 1 interrupt
Capture2 interrupt
USART synchronous slave transmit interrupt
USART synchronous slave receive interrupt
Other peripherals can not wake from Sleep because during Sleep, no on-chip Q clocks are present

79. Programming the PIC17C4X in “C”
The Microchip development environment includes a compiler for the “C” programming language
Included with the compiler a libraries for manipulating the special functions of the PIC microcontrollers
These libraries consist of header files which define the registers and variables necessary and C functions which perform some of the needed actions
The main header file for each processor defines the all of the registers and individual bits that have been discussed - thus it is always possible for you to manipulate the hardware registers and setup the functions directly

80. P17c44.h
#pragma nolist /*
* MPLAB-C17 v2.10 PIC17C44 processor header *
* (c) Copyright Microchip Technology, All rights reserved
* */
#ifndef __17C44_H
#define __17C44_H
extern near unsigned char INDF0;
extern near unsigned char FSR0;
extern volatile near unsigned char PCL;
extern near unsigned char PCLATH;
extern volatile near unsigned char ALUSTA;
extern volatile near struct {
unsigned C:1;
unsigned DC:1;
unsigned Z:1;
unsigned OV:1;
unsigned FS0:1;
unsigned FS1:1;
unsigned FS2:1;
unsigned FS3:1;
} ALUSTAbits ;
extern near unsigned char T0STA;
extern near struct {
unsigned :1;
unsigned T0PS0:1;
unsigned T0PS1:1;
unsigned T0PS2:1;
unsigned T0PS3:1;
unsigned T0CS:1;
unsigned T0SE:1;
unsigned INTEDG:1;
} T0STAbits ;
extern volatile near unsigned char CPUSTA;
extern volatile near struct {
unsigned NOT_BOR:1;
unsigned NOT_POR:1;
unsigned NOT_PD:1;
unsigned NOT_TO:1;
unsigned GLINTD:1;
unsigned STKAV:1;
} CPUSTAbits ;
extern volatile near unsigned char INTSTA;
unsigned INTE:1;
unsigned T0IE:1;
unsigned T0CKIE:1;
unsigned PEIE:1;
unsigned INTF:1;
unsigned T0IF:1;
unsigned T0CKIF:1;
unsigned PEIF:1;
} INTSTAbits ;
extern near unsigned char INDF1;
extern near unsigned char FSR1;
extern near unsigned char WREG;
extern volatile near unsigned TMR0;
extern volatile near unsigned char TMR0L;
extern volatile near unsigned char TMR0H;
extern near unsigned TBLPTR;
extern near unsigned char TBLPTRL;
extern near unsigned char TBLPTRH;
extern near unsigned char BSR;
extern volatile far unsigned char PORTA;

81. P17c44.h (cont.) extern volatile far union {
struct {
unsigned RA0:1;
unsigned RA1:1;
unsigned RA2:1;
unsigned RA3:1;
unsigned RA4:1;
unsigned RA5:1;
unsigned :1;
unsigned NOT_RBPU:1;
} ;
unsigned INT:1;
unsigned T0CKI:1;
} PORTAbits ;
extern far unsigned char DDRB;
extern far struct {
unsigned RB0:1;
unsigned RB1:1;
unsigned RB2:1;
unsigned RB3:1;
unsigned RB4:1;
unsigned RB5:1;
unsigned RB6:1;
unsigned RB7:1;
} DDRBbits ;
extern volatile far unsigned char PORTB;
extern volatile far struct {
} PORTBbits ;
extern far unsigned char RCSTA;
extern far struct {
unsigned RX9D:1;
unsigned OERR:1;
unsigned FERR:1;
unsigned :1;
unsigned CREN:1;
unsigned SREN:1;
unsigned RX9:1;
unsigned SPEN:1;
} RCSTAbits ;
extern far unsigned char RCREG;
extern far unsigned char TXSTA;
unsigned TX9D:1;
unsigned TRMT:1;
unsigned :2;
unsigned SYNC:1;
unsigned TXEN:1;
unsigned TX9:1;
unsigned CSRC:1;
} TXSTAbits ;
extern far unsigned char TXREG;
extern far unsigned char SPBRG;
extern near unsigned PROD;
extern near unsigned char PRODL;
extern near unsigned char PRODH;
extern far unsigned char DDRC;
unsigned RC0:1;
unsigned RC1:1;
unsigned RC2:1;
unsigned RC3:1;
unsigned RC4:1;
unsigned RC5:1;
unsigned RC6:1;
unsigned RC7:1;
} DDRCbits ;
extern volatile far unsigned char PORTC;

82. P17c44.h (cont.) extern volatile far union { struct { unsigned RD0:1;
} ;
unsigned AD8:1;
unsigned AD9:1;
unsigned AD10:1;
unsigned AD11:1;
unsigned AD12:1;
unsigned AD13:1;
unsigned AD14:1;
unsigned AD15:1;
} PORTDbits ;
extern far unsigned char DDRE;
extern far struct {
unsigned RE0:1;
unsigned RE1:1;
unsigned RE2:1;
} DDREbits ;
extern volatile far unsigned char PORTE;
unsigned ALE:1;
unsigned NOT_OE:1;
unsigned NOT_WR:1;
} PORTEbits ;
extern volatile far union {
struct {
unsigned RC0:1;
unsigned RC1:1;
unsigned RC2:1;
unsigned RC3:1;
unsigned RC4:1;
unsigned RC5:1;
unsigned RC6:1;
unsigned RC7:1;
} ;
unsigned AD0:1;
unsigned AD1:1;
unsigned AD2:1;
unsigned AD3:1;
unsigned AD4:1;
unsigned AD5:1;
unsigned AD6:1;
unsigned AD7:1;
} PORTCbits ;
extern far unsigned char DDRD;
extern far struct {
unsigned RD0:1;
unsigned RD1:1;
unsigned RD2:1;
unsigned RD3:1;
unsigned RD4:1;
unsigned RD5:1;
unsigned RD6:1;
unsigned RD7:1;
} DDRDbits ;
extern volatile far unsigned char PORTD;

83. P17c44.h (cont.) extern far struct { extern far unsigned char PIR;
unsigned RCIF:1;
unsigned TXIF:1;
unsigned CA1IF:1;
unsigned CA2IF:1;
unsigned TMR1IF:1;
unsigned TMR2IF:1;
unsigned TMR3IF:1;
unsigned RBIF:1;
} PIRbits ;
extern far unsigned char PIE;
unsigned RCIE:1;
unsigned TXIE:1;
unsigned CA1IE:1;
unsigned CA2IE:1;
unsigned TMR1IE:1;
unsigned TMR2IE:1;
unsigned TMR3IE:1;
unsigned RBIE:1;
} PIEbits ;
extern volatile far unsigned char TMR1;
extern volatile far unsigned char TMR2;
extern volatile far unsigned TMR3;
extern volatile far unsigned char TMR3L;
extern volatile far unsigned char TMR3H;
extern far unsigned char PR1;
extern far unsigned char PR2;
extern volatile far unsigned CA1;
extern volatile far unsigned char PR3L;
extern volatile far unsigned char CA1L;
extern far unsigned PR3;
extern volatile far unsigned char PR3H;
extern volatile far unsigned char CA1H;
extern far unsigned char PW1DCL;
extern far struct {
unsigned :6;
unsigned DC0:1;
unsigned DC1:1;
} PW1DCLbits ;
extern far unsigned char PW2DCL;
unsigned :5;
unsigned TM2PW2:1;
} PW2DCLbits ;
extern far unsigned char PW1DCH;
unsigned DC2:1;
unsigned DC3:1;
unsigned DC4:1;
unsigned DC5:1;
unsigned DC6:1;
unsigned DC7:1;
unsigned DC8:1;
unsigned DC9:1;
} PW1DCHbits ;
extern far unsigned char PW2DCH;
} PW2DCHbits ;
extern volatile far unsigned char CA2L;
extern volatile far unsigned CA2;
extern volatile far unsigned char CA2H;
extern far unsigned char TCON1;

84. P17c44.h (cont.)
extern far struct {
unsigned TMR1CS:1;
unsigned TMR2CS:1;
unsigned TMR3CS:1;
unsigned T16:1;
unsigned CA1ED0:1;
unsigned CA1ED1:1;
unsigned CA2ED0:1;
unsigned CA2ED1:1;
} TCON1bits ;
extern far unsigned char TCON2;
extern far union {
struct {
unsigned TMR1ON:1;
unsigned TMR2ON:1;
unsigned TMR3ON:1;
unsigned CA1:1;
unsigned PWM1ON:1;
unsigned PWM2ON:1;
unsigned CA1OVF:1;
unsigned CA2OVF:1;
} ;
unsigned :3;
unsigned NOT_PR3:1;
} TCON2bits ;
#pragma varlocate sfr 0 PORTA
... long list of varlocates removed
#pragma varlocate sfr 3 TCON2bits
/* Declare the function pointers the interrupt handlers will use.
* We can put these in the general purpose header since this
* doesn't allocate any space. If the user doesn't link in the
* interrupt module for this processor, these don't do anything. */
extern void (*fpINT)(void);
extern void (*fpTMR0) (void);
extern void (*fpT0CKI) (void);
extern void (*fpPIV)(void);
/* Macros for installing interrupt functions. */
#define Install_INT(isr) { fpINT = isr; }
#define Install_TMR0(isr) { fpTMR0 = isr; }
#define Install_T0CKI(isr){ fpT0CKI = isr; }
#define Install_PIV(isr) { fpPIV = isr; }
/* Define some useful macros for inline assembly stuff */
#define Nop() {_asm nop _endasm}
#define ClrWdt() {_asm clrwdt _endasm}
#define Sleep() {_asm sleep _endasm}
#define Rrcf(f) {_asm banksel f rrcf f _endasm}
#define Rrncf(f) {_asm banksel f rrncf f _endasm}
#define Rlcf(f) {_asm banksel f rlcf f _endasm}
#define Rlncf(f) {_asm banksel f rlncf f _endasm}
#define Swapf(f) {_asm banksel f swapf f _endasm}
#define n_Rrcf(f) {_asm rrcf f _endasm}
#define n_Rrncf(f) {_asm rrncf f _endasm}
#define n_Rlcf(f) {_asm rlcf f _endasm}
#define n_Rlncf(f) {_asm rlncf f _endasm}
#define n_Swapf(f) {_asm swapf f _endasm}
#endif
#pragma list

85. Interrupt Functions

86. int16.h
#pragma nolist
/********************************************************************
* PICmicro C Libraries V *
* Written and Tested using MPLABC V *
*********************************************************************
* Filename: int16.h *
* Date: April *
* File Version: *
* Functions: *
* Header file *
* Revision History: *
* V Beta release of Peripheral Libraries for V *
* V Release of Peripheral Libraries for V *
* V Release of Peripheral Libraries for V *
* Notes: *
* ROM usage varies depending on specified device *
********************************************************************/
#ifndef __INT16_H
#define __INT16_H
// Global Interrupt Function Declarations
void Enable(void); // Enable global interrupts
void Disable(void); // Disable global interrupts
// RA0/INT Config Bit Defines
#define INT_ON 0b // RA0/INT interrupts on
#define INT_OFF 0b // RA0/INT interrupts off
#define INT_RISE_EDGE 0b // Interrupt on rising edge
#define INT_FALL_EDGE 0b // Interrupt on falling edge
// RAO/INT Function Declarations
void OpenRA0INT(static unsigned char); // Configure RA0/INT interrupt
void CloseRA0INT(void); // Disable RA0/INT interrupt
#endif
#pragma list

87. I/O Port Functions

88. I/O Port Functions (cont.)

89. Portb16.h
#pragma nolist
/********************************************************************
* PICmicro C Libraries V *
* Written and Tested using MPLABC V *
*********************************************************************
* Filename: portb16.h *
* Date: April *
* File Version: *
* Functions: *
* Header file *
* Revision History: *
* V Beta release of Peripheral Libraries for V *
* V Release of Peripheral Libraries for V *
* V Release of Peripheral Libraries for V *
* Notes: *
* ROM usage varies depending on specified device *
********************************************************************/
#ifndef __PORTB16_H
#define __PORTB16_H
// PORTB Config Bit Defines
#define PORTB_CHANGE_INT_ON 0b // PORTB interrupts on
#define PORTB_CHANGE_INT_OFF 0b // PORTB interrupts off
#define PORTB_PULLUPS_ON 0b // PORTB pullups on
#define PORTB_PULLUPS_OFF 0b // PORTB pullups off
// PORTB Function Declarations
void OpenPORTB(static unsigned char); // Configure PORTB interrupts,resistors
void ClosePORTB(void); // Disable PORTB interrupts, resistors
void EnablePullups(void); // Enable PORTB resistors
void DisablePullups(void); // Disable PORTB resistors
#endif
#pragma list

90. Pulse Width Modulation Functions

91. Pulse Width Modulation Functions (cont.)

92. Pwm16.h
#pragma nolist
/********************************************************************
* PICmicro C Libraries V *
* Written and Tested using MPLABC V *
*********************************************************************
* Filename: pwm16.h *
* Date: April *
* File Version: *
* Functions: *
* Header file *
* Revision History: *
* V Beta release of Peripheral Libraries for *
* V Release of Peripheral Libraries for V *
* V Release of Peripheral Libraries for V *
* Notes: *
* ROM usage varies depending on specified device *
********************************************************************/
#ifndef __PWM16_H
#define __PWM16_H
// PWM Duty Cycle union
union PWMDC {
unsigned int lpwm;
char bpwm[2]; };
// PWM Config Bit Defines
#define T1_SOURCE 0b // Timer1 clock source
#define T2_SOURCE 0b // Timer2 clock source
// PWM1 Function Declarations
void OpenPWM1(static char); // Configure clock, period and interrupt
void SetDCPWM1(static unsigned int); // Write duty cycle
void ClosePWM1(void); // Disable PWM and interrupt
// PWM2 Function Declarations
void OpenPWM2(static unsigned char,char); // Configure clock, period and interrupt
void SetDCPWM2(static unsigned int); // Write duty cycle
void ClosePWM2(void); // Disable PWM and interrupt

93. Pwm16.h (cont.)
#if defined(__17C752)||defined(__17C756)||defined(__17C756A)||defined(__17C766)||defined(__17C762)
// PWM3 Function Declarations
void OpenPWM3(static unsigned char,char); // Configure clock, period and interrupt
void SetDCPWM3(static unsigned int); // Write duty cycle
void ClosePWM3(void); // Disable PWM and interrupt
#endif
#pragma list

94. Timer Functions

95. Timer Functions (cont.)

96. Timer Functions (cont.)

97. Timers16.h #pragma nolist
/********************************************************************
* PICmicro C Libraries V *
* Written and Tested using MPLABC V *
*********************************************************************
* Filename: timers16.h *
* Date: April *
* File Version: *
* Functions: *
* Header file *
* Revision History: *
* V Beta release of Peripheral Libraries for V *
* V Release of Peripheral Libraries for V *
* V Release of Peripheral Libraries for V *
* Notes: *
* ROM usage varies depending on specified device *
********************************************************************/
#ifndef __TIMERS16_H
#define __TIMERS16_H
// Union for reading and writing timers
union Timers {
unsigned int lt;
char bt[2]; };
// Timer Config Bit Defines
#define TIMER_INT_ON 0b // Interrupts on
#define TIMER_INT_OFF 0b // Interrupts off
// Timer0 Config Bit Defines
#define T0_EDGE_FALL 0b // External falling edge clocks timer
#define T0_EDGE_RISE 0b // External rising edge clocs timer
#define T0_SOURCE_EXT 0b // External clock source
#define T0_SOURCE_INT 0b // Internal clock source

98. Timers16.h (cont.) #define T0_PS_1_1 0b11100001 // Prescaler 1:1
// Timer0 Function Declarations
void OpenTimer0(static unsigned char); // Configures Timer0
void CloseTimer0(void); // Disables Timer0
unsigned int ReadTimer0(void); // Reads Timer0 registers
void WriteTimer0(static unsigned int); // Writes Timer0 registers
// Timer1 Config Bit Defines
#define T1_SOURCE_INT 0b // Internal clock source
#define T1_SOURCE_EXT 0b // External clock source
#define T1_T2_8BIT 0b // 8-bit mode
#define T1_T2_16BIT 0b // 16-bit mode
// Timer1 Function Declarations
void OpenTimer1(static unsigned char); // Configures Timer1
void CloseTimer1(void); // Disables Timer1
unsigned char ReadTimer1(void); // Reads Timer1
void WriteTimer1(static unsigned char); // Writes Timer1
// Timer1:Timer2 Function Declarations
unsigned int ReadTimer1_16(void); // Reads 16-bit Timer2:Timer1
void WriteTimer1_16(static unsigned int); // Writes 16-bit Timer2:Timer1

99. Timers16.h (cont.) // Timer2 Config Bit Defines
#define T2_SOURCE_INT 0b // Internal clock source
#define T2_SOURCE_EXT 0b // External clock source
// Timer2 Function Declarations
void OpenTimer2(static unsigned char); // Configures Timer2
void CloseTimer2(void); // Disables Timer2
unsigned char ReadTimer2(void); // Reads Timer2
void WriteTimer2(static unsigned char); // Writes Timer2
// Timer3 Config Bit Defines
#define T3_SOURCE_INT 0b // Internal clock source
#define T3_SOURCE_EXT 0b // External clock source
// Timer3 Function Declarations
void OpenTimer3(static unsigned char); // Configures Timer3
void CloseTimer3(void); // Disables Timer3
unsigned int ReadTimer3(void); // Reads Timer3
void WriteTimer3(static unsigned int); // Writes Timer3
#endif
#pragma list

100. Capture Input Functions

101. Capture Input Functions (cont.)

102. Captur16.h #pragma nolist
/********************************************************************
* PICmicro C Libraries V *
* Written and Tested using MPLABC V *
*********************************************************************
* Filename: captur16.h *
* Date: April *
* File Version: *
* Functions: *
* Header File *
* Revision History: *
* V Beta release of Peripheral Libraries for *
* V Release of Peripheral Libraries for V *
* V Release of Peripheral Libraries for V *
* Notes: *
* ROM usage varies depending on specified device *
********************************************************************/
#ifndef __CAPTUR16_H
#define __CAPTUR16_H
// Capture Status Byte
struct capstatus {
unsigned Cap1OVF:1;
unsigned Cap2OVF:1;
unsigned Cap3OVF:1;
unsigned Cap4OVF:1;
unsigned :4; };
// Union for capture
union CapResult
unsigned int lc;
char bc[2];

103. Captur16.h (cont.) // Capture Config Bit Defines
#define CAPTURE_INT_ON 0b // Interrupt on
#define CAPTURE_INT_OFF 0b // Interrupt off
// Capture1 Config Bit Defines
#define C1_EVERY_FALL_EDGE 0b // Every falling edge
#define C1_EVERY_RISE_EDGE 0b // Every rising edge
#define C1_EVERY_4_RISE_EDGE 0b // Every 4th rising edge
#define C1_EVERY_16_RISE_EDGE 0b // Every 16th rising edge
#define CAPTURE1_PERIOD 0b // Make capture1 a period
#define CAPTURE1_CAPTURE 0b // Make capture1 a capture
// Capture1 Function Declaration
void OpenCapture1(static unsigned char); // Setup capture1
unsigned int ReadCapture1(void); // Read the capture1 results
void CloseCapture1(void); // Disable capture1
// Capture2 Config Bit Defines
#define C2_EVERY_FALL_EDGE 0b // Every falling edge
#define C2_EVERY_RISE_EDGE 0b // Every rising edge
#define C2_EVERY_4_RISE_EDGE 0b // Every 4th rising edge
#define C2_EVERY_16_RISE_EDGE 0b // Every 16th rising edge
// Capture2 Function Declaration
void OpenCapture2(static unsigned char); // Setup capture2
unsigned int ReadCapture2(void); // Read the capture2 results
void CloseCapture2(void); // Disable capture2
// Capture3 Config Bit Defines
#define C3_EVERY_FALL_EDGE 0b // Every falling edge
#define C3_EVERY_RISE_EDGE 0b // Every rising edge
#define C3_EVERY_4_RISE_EDGE 0b // Every 4th rising edge
#define C3_EVERY_16_RISE_EDGE 0b // Every 16th rising edge

104. Captur16.h (cont.)
#if defined(__17C752)||defined(__17C756)||defined(__17C756A)||defined(__17C766)||defined(__17C762)
// Capture3 Function Declaration
void OpenCapture3(static unsigned char); // Setup capture3
unsigned int ReadCapture3(void); // Read the capture3 results
void CloseCapture3(void); // Disable capture3
// Capture4 Config Bit Defines
#define C4_EVERY_FALL_EDGE 0b // Every falling edge
#define C4_EVERY_RISE_EDGE 0b // Every rising edge
#define C4_EVERY_4_RISE_EDGE 0b // Every 4th rising edge
#define C4_EVERY_16_RISE_EDGE 0b // Every 16th rising edge
// Capture4 Function Declaration
void OpenCapture4(static unsigned char); // Setup capture4
unsigned int ReadCapture4(void); // Read the capture4 results
void CloseCapture4(void); // Disable capture4
#endif
#pragma list

105. Reset Functions

106. Reset Functions (cont.)

107. Reset.h (cont.) #pragma nolist
/********************************************************************
* PICmicro C Libraries V *
* Written and Tested using MPLABC V *
*********************************************************************
* Filename: reset16.h *
* Date: April *
* File Version: *
* Functions: *
* Header file *
* Revision History: *
* V Beta release of Peripheral Libraries for V *
* V Release of Peripheral Libraries for V *
* V Release of Peripheral Libraries for V *
* Notes: *
* ROM usage varies depending on specified device *
********************************************************************/
#ifndef __RESET16_H
#define __RESET16_H
#define WDT_ENABLED
#define BOR_ENABLED
#if defined(__17C756)
char isMCLR(void); // MCLR reset?
void StatusReset(void); // Reset the POR and BOR bits
#endif
#if defined(BOR_ENABLED)
char isBOR(void); // BOR reset?
#if defined(WDT_ENABLED)
char isWDTTO(void); // WDT timeout during operation?
char isWDTWU(void); // WDT timeout during sleep?
char isPOR(void); // POR reset?
char isWU(void); // Wakeup during sleep?
#pragma list

108. Intel 8051 Microcontroller
The Intel bit microcontroller is one of the most frequently used
There are a number of different variations, some even from other manufacturers an example implementation (8XC51FX) includes:
12/24/33 MHz operation
8K/16K/32K On-chip program memory
256 bytes On-Chip data RAM
64K of external program and 64K of external data memory space
Three 16-bit timer/counters
Programmable counter array with:
High Speed Output
Compare/Capture
Pulse Width Modulator
Watchdog Timer capability
32 programmable I/O lines
7 interrupt sources

109. Intel 8051 Microcontroller

110. Intel 8051 Microcontroller

111. Intel 8051 Microcontroller Instruction Set

112. Intel 8051 Microcontroller Instruction Set (cont.)

113. Intel 8051 Microcontroller Architecture

114. Intel 8051 Microcontroller Pinout

115. Intel 80296SA Microcontroller
A 16-bit microcontroller
50MHz operation
6Mbytes of address space
512 bytes of register RAM - 2Kbytes of Code/Data RAM
32 I/O ports
19 Interrupt sources with 14 programmable priorities
4 External interrupt pins (one NMI pin)
2 16-bit timer/counters
3 Pulse Width Modulator outputs
Full-duplex serial port
4 high-speed capture/compare channels
80 Ns multiply accumulate
880 Ns 32/16 bit unsigned division

116. Intel 80296SA Microcontroller Architecture

117. Intel 80296SA Microcontroller Pinout

118. Atmel AT90S1200 Microcontroller
8-bit RISC microcontroller (89 instructions)
32 x 8 registers (data RAM)
1K byte on-chip program Flash memory
64 bytes on-chip EEPROM
One 8-bit timer/counter with separate prescaler
On-chip analog comparator
Programmable watchdog timer with on-chip oscillator
SPI serial interface for in-system programming
15 programmable I/O lines
Low-power idle and power down modes
External and Internal interrupt sources

119. Atmel AT90S1200 Microcontroller Architecture

120. Atmel AT90S1200 Microcontroller Pinout

121. Motorola MMC2001 Microcontroller
32-bit RISC processor core
On-chip 256 Kbyte ROM
On-chip 32 Kbyte SRAM with battery backup supply support
Support for 32 interrupt sources
External Interface Module:
transfers information between processor and external memory or peripherals
20 address and 16 data lines
Bus watchdog timer
On-chip UART and separate SPI interface modules
16-bit I/O port with keyboard support
8-bit I/O port with support for edge/level sensitive external interrupts
Six independent PWM channels
Timer/Reset Module:
Time-of-day timer runs from external crystal
Watchdog timer
Periodic interrupt timer

122. Motorola MMC2001 Microcontroller Architecture

123. Motorola MMC2001 Microcontroller Pinout