1. 1-1 Ethernet Ethernet Controller How do you interface with an Ethernet PHY?

2. 1-2 Ethernet Controller Block Diagram MAC module EFE module Rx FIFO (2048b) Tx FIFO (128b) Control State Machine Control Status DMA Controller Tx 110 Rx 110 10BT10BT MIIMII 10/100 MAC Address Filtering/ Statistics To/From PHY

3. 1-3 Ethernet MAC-PHY Media- Independent Interface (MII) MDIO MDCLK COL Collision Carrier Sense CRS TXD TXEN RXDV RXD TXER RXER TXCLK RXCLK Rx Data Clocks for Tx/Rx “Data Ready” Tx/Rx Error Net+ARM MAC PHY Tx Data PHY Mgt (e.g., setup) (Remainder of MII pins are V or GND.)

4. 1-4 PHY Management Software sends/receives a serial stream on MDIO, clocked by MDCLK. Stream consists of management frames, each causing a PHY register to be read or written. –Registers 0 – 1: predefined, required –Registers 2 – 7: predefined, optional –Registers 8 – 15: reserved –Registers 16 – 31: vendor-specific

5. 1-5 Culture – Management Frame Format Preamble – 32 consecutive 1’s FS – start of frame OP – read or write PHY Address – 0 to 31; usually specified via PHY pins Register Address – 0 to 31 TA – Turnaround: separator between frame header and data Data – 16 bits Ends with high-impedance idle state PreambleFSOPPHY AddrReg AddrTADATA READ32 1’s0110xxxxx 00xxxxxxxxxxxxxxxx WRITE32 1’s01 xxxxx 00xxxxxxxxxxxxxxxx

6. 1-6 MII PHY Predefined Registers 0 – Control 1 – Status 2, 3 – PHY ID (manufacturer, model, rev; optional) 4 – Auto Negotiation Advertisement (optional) 5 – Auto Negotiation Link Partner (optional) 6 – Auto Negotiation Expansion (optional) 7 – Auto Negotiation Next Page Xmit (optional) Consult your PHY documentation for register usage

7. 1-7 Managing the PHY through MII PreambleFSOPPHY AddrReg AddrTADATA READ32 1’s0110xxxxx 00xxxxxxxxxxxxxxxx WRITE32 1’s01 xxxxx 00xxxxxxxxxxxxxxxx From MII Address Register (0xFF800544) From MII Write Data Register (0xFF800548) Initiate by MII Command Register (0xFF800540) To MII Read Data Register (0xFF80054C) Writes are initiated by writing to MWTD. Read/write done when BUSY in MII Indicators Register (0xFF800550) returns to 0.

8. 1-8 Auto-Negotiation Exchange configuration information between two ends of a link segment and automatically select the highest common performance mode. When: 1.Power up 2.Reset (hardware and software) 3.Link failure and comes back up 4.Software re-start

9. 1-9 Parallel Detection When partner does not support Auto-Negotiation Automatically detect the presence of either link pulse (10 Mbps) or idle symbol (100 Mbps) and set speed accordingly. Set Half mode.