1. Khaled A. Al-Utaibi alutaibi@uoh.edu.sa

2.  8086 Pinout & Pin Functions  Minimum & Maximum Mode Operations  Microcomputer System Design  Minimum Mode Connections

3.  AD 15 -AD 0 : − These lines represent time multiplexed address and data bus lines. − During T 1, they represent address lines A 15 -A 0. − During T 2, T 3, T w, T 4, they represent data lines D 15 -D 0.

4.  A 19 /S 6 -A 16 /S 3 : − These lines represent time multiplexed address and status lines. − During T 1, they represent address lines A 19 -A 16. − During T 2, T 3, T w, T 4, they represent status signals S 6 -S 3.

5.  ALE (Address Latch Enable ): − This signal is a HIGH pulse active during T1 of any bus cycle. − It is provided by the processor to latch the address lines during T 2, T 3, T w, T 4 cycles.

6.  READY: − Active HIGH signal. − This is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer. − If it is set LOW, the processor enters into wait states and remains idle. − If it is set HIGH, it has no effect on the operation of the processor.

7.  INTR (Interrupt Request): − It is used to request a hardware interrupt. − If it is held HIGH when IF = 1, the processor enters an interrupt acknowledge cycle after the current instruction complete execution.  INTA (Interrupt Acknowledge): − This signal is a response to the INTR input pin.  NMI (Non-Maskable Interrupt): − Similar to INTR except that NMI does not check if the IF=1.

8.  TEST: − Active LOW signal. − This input is examined by the WAIT instruction. − If the TEST input is LOW execution continues, − Otherwise the processor waits in an IDLE state. − Usually this pin is connected to the 8087 FP coprocessor.

9.  RESET: − RESET causes the processor to immediately terminate its present activity. − The signal must be active HIGH for at least four clock cycles. − The processor restarts execution, when RESET returns LOW.

10.  CLK (Clock): − CLOCK provides the basic timing for the processor and bus controller. − It is asymmetric with a 33% duty cycle (HIGH for 1/3 of the clocking period and LOW for 2/3 of the clocking period) to provide proper internal timing.

11.  BHE/S 7 (Bus High Enable): − Active low signal. − It is used together with A0 during T1 to select whole word, odd byte, even byte or none. Data SelectedA0A0 BHE Word (D 15 -D 0 )00 Odd Byte (D 15 -D 8 )10 Even Byte (D 7 -D 0 )01 None11

12.  M/IO (Memory/IO): − This pin is used to distinguish a memory access from an I/O access.  HIGH  Memory access  LOW  I/O access − It indicates that the processor address bus contains either a memory address or an I/O port address.

13.  RD (READ): − Active LOW signal − Read strobe indicates that the processor is performing a memory or I/O read cycle, depending on the state of the M/IO signal.  WR (WRITE): − Active LOW signal − Write strobe indicates that the processor is performing a memory write or I/O write cycle, depending on the state of the M/IO signal.

14.  DT/R (Data Transmit/Receive): − Needed in minimum system that desires to use a data bus transceiver. − It is used to control the direction of data flow through the transceiver. − HIGH  Transmit − LOW  Receive

15.  DEN( Data Enable ): − Active LOW signal − Needed in minimum system that desires to use a data bus transceiver. − It is used as an output enable for the transceiver. − HIGH  Enable − LOW  Disable

16.  HOLD: − This input requests a direct memory access (DMA) − If this input is HIGH, the processor stops executing & places its address, data, and control bust at high-impedance state. − If this input is LOW, the processor executes software normally.  HLDA (Hold Acknowledge): − This signal indicates that the processor has entered the hold state

17.  VCC (+5V Power Supply)  GND (Ground)  MN/MX (Minimum/Maximum): − indicates what mode the processor is to operate in. − HIGH  minimum mode. − LOW  maximum mode.

18.  The 8086 can operate in either one of two modes of operation: − (1) Minimum Mode − (2) Maximum Mode  Minimum Mode: − The simplest and least expensive mode. − All the control signals for memory & I/O operations are generated by the processor.  Maximum Mode: − Allows the system to use an external coprocessor such as 8087 (floating-point coprocessor). − Some of the control signals must be externally generated (requires an external bus controller 8288)

19.  A very simple microcomputer system consists of the following part: − (1) 8284A Clock Generator (15 MHz Crystal) − (2) 8086 Microprocessor(Minimum Mode) − (3) Bus System (Demultiplexed and Buffered) − (4) Memory System (ROM & RAM Modules) − (5) I/O System (Switches and LEDs)

21.  Basic Connections: − GND: connect to 0V. − VCC: connect to 5V. − MN/MX’: connect to 5V (minimum mode). − NMI & INTR: connect to 0V (no support for interrupts). − CLK: connect to the CLK output of the clock generator. − HOLD: connect to 0V (no direct memory access). − TEST’: connect to 0V (no wait for co-processor). − READY: connect to 5V (no wait cycles for slow devices). − RESET: connect to RESET output of the clock generator.

22. 5V 0V 5V RESET (8084A) 0V (8284A) CLK