1. ELEC 256 / Saif Zahir UBC / 2000 Counters An (up/down) k-bit counter produces a sequence of k-bit binary numbers in a response to a COUNT pulse. A k-bit counter can have up to 2 k different states Example: 74163 4-bit synchronous counter QA QB QC QD 163 RCO P T A B C D LOAD CLR CLK 0 1 0 1 0 10 1 15 3 4 5 6 14 QA 12 QC 11 QD 13 QB 9 1 CLR 10 7 2 CLK LogicWorks Timing Simulation 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 1

2. ELEC 256 / Saif Zahir UBC / 2000 Design of a 3-Bit Up-Counter 000 001 010 011 100 101 110 111 Present Next FF inputs C B A C+ B+ A+ TC TB TA 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 0 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 1 0 0 1 1 1 1 0 0 0 1 1 1 A CB 00011110 0 1 A CB 00011110 0 1 A CB 00011110 0 1 1111 1111 0000 1111 0000 0110 TA=1TB=ATC=AB Next-state Logic

3. ELEC 256 / Saif Zahir UBC / 2000 Design of a 3-Bit Up-Counter Flipflop input equations TA = 1 TB = A TC = AB 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 TQ S R TQ S R TQ S R A BC \Reset Count 1 1

4. ELEC 256 / Saif Zahir UBC / 2000 Design of a 3-Bit Up-Counter 000 001 010 011 100 101 110 111 Present Next FF inputs C B A C+ B+ A+ DC DB DA 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 A CB 00011110 0 1 A CB 00011110 0 1 A CB 00011110 0 1 1111 0000 0110 1001 0011 0101 da = Adb = Ab + aBdc = cB+cA+Cba Use D flipflops

5. ELEC 256 / Saif Zahir UBC / 2000 Up-Counter Using D Flipflops da = Adb = Ab + aBdc = cB+cA+Cba DQ S R DQ S R DQ S R A BC \Reset Count AB T-FF realization is more efficient - requires less additional combinational logic

6. ELEC 256 / Saif Zahir UBC / 2000 Complex-Counter Design Procedure 1. From specification, draw state-transition diagram to show the desired sequence to be realized by counter. 2. Choose flipflop type, then use FF excitation-table to derive next-state and FF-input equations. Example: Design the following 5-state counter 000 010 011 101 110 C B A C+ B+ A+ TC TB TA 0 0 0 0 1 0 0 1 0 0 0 1 X X X X X X 0 1 0 0 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 0 0 X X X X X X 1 0 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 1 1 1 X X X X X X PSNSFF-inputs Remark: The states that do not appear in the counter squence are treated as don’t care’s! Using K-maps: tc = Ac + aC tb = a + B + c ta = AbC + Bc

7. ELEC 256 / Saif Zahir UBC / 2000 Self-Starting Counters In previous example, a problem may arise of the counter starts in one of the unused states (001, 100, or 111). Since these states were used as don’t-cares, then depending on how these don’t cares were used, counter may exhibit unwanted behavior. 000 010 011 101 110 001 100 111 000 010 011 101 110 111 001 100 Bad Design Counter may sequence through unwanted states forever (unless, reset). Better Design: If starts in an unwanted state, counter will go (atmost after one clock-cycle) into its normal state sequence.

8. ELEC 256 / Saif Zahir UBC / 2000 Self-Starting Counters C B A C+ B+ A+ TC TB TA 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 1 1 0 0 1 0 0 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 0 0 0 1 1 1 1 1 1 0 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 1 1 1 1 0 1 0 1 0 PSNSFF-inputs 000 010 011 101 110 111 001 100 A CB 00011110 0 1 A CB 00011110 0 1 A CB 00011110 0 1 0011 1100 1011 1111 0101 0001 tc = Ac + aC Next-state Logic tb = a + B + cta = AbC + Bc Another possible state diagram for a self-starting counter

9. ELEC 256 / Saif Zahir UBC / 2000 Counter Design with RS Flipflops Example: Design the 5-state self-starting counter using RS flipflops C B A C+ B+ A+ RC SC RB SB RA SA 0 0 0 0 1 0 X 0 0 1 X 0 0 0 1 X X X X X X X X X 0 1 0 0 1 1 X 0 0 X 0 1 0 1 1 1 0 1 0 1 1 0 0 X 1 0 0 X X X X X X X X X 1 0 1 1 1 0 0 X 0 1 1 0 1 1 0 0 0 0 1 0 1 0 X 0 1 1 1 X X X X X X X X X PSNSFF-inputs Q Q + R S 0 0 X 0 0 1 1 0 1 1 0 X A CB 00011110 0 1 A CB 00011110 0 1 A CB 00011110 0 1 XX1X X0X0 001X X1X0 X0XX X0X1 sc = a sb = B sa = bC A CB 00011110 0 1 A CB 00011110 0 1 A CB 00011110 0 1 000X X1XX 1X0X X0X1 010X XXX0 tc = A tb = ab+ac ta = c RS-FF excitation table

10. ELEC 256 / Saif Zahir UBC / 2000 Counter Design with JK Flipflops Example: Design the 5-state self-starting counter using JK flipflops C B A C+ B+ A+ JC KC JB KB JA KA 0 0 0 0 1 0 0 X 1 X 0 X 0 0 1 X X X X X X X X X 0 1 0 0 1 1 0 X X 0 1 X 0 1 1 1 0 1 1 X X 1 X 0 1 0 0 X X X X X X X X X 1 0 1 1 1 0 X 0 1 X X 1 1 1 0 0 0 0 X 1 X 1 0 X 1 1 1 X X X X X X X X X PSNSFF-inputs Q Q + J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0 A CB 00011110 0 1 A CB 00011110 0 1 A CB 00011110 0 1 XX1X XXX0 X01X X1XX XXXX X0X1 kc = A kb = a + c ka = C jc = a jb = 1 ja = bC JK-FF excitation table A CB 00011110 0 1 A CB 00011110 0 1 A CB 00011110 0 1 00XX X1XX 1XXX XXX1 010X XXXX

11. ELEC 256 / Saif Zahir UBC / 2000 Counter Design and Timing JK-FF Realization Timing Diagram

12. ELEC 256 / Saif Zahir UBC / 2000 Storage Registers CLK CLR D3 D2 D1 D0 Q3 Q2 Q1 Q0 171 D R Q D R Q D R Q D R Q D3 D2 D1 D0 Q3 Q2 Q1 Q0 CLK CLR S=1 K-bit storage register can be realized by the parallel connection of K D-type flipflops RS or JK flipflops can be used instead as long as they implement the D-FF function! TTL 74171 package: Quadruple D-type Flipflop with Clear

13. ELEC 256 / Saif Zahir UBC / 2000 Registers with Input Enable CLK CLR D3 D2 D1 D0 Q3 Q2 Q1 Q0 171 CLK EN D3 D2 D1 D0 377 Q3 Q2 Q1 Q0 Q7 Q6 Q5 Q4 D7 D6 D5 D4 EN D0D0 D7D7 D0D0 D7D7 System Clock 2:1 0 MUX 1 Select Data Bus 74377 In the 74171, register contents may change with every positive clock edge. In the 74377, registers contents change (after the psoitive edge of CLK) only if EN is asserted (EN=0) Potential use of 377 packages in a computer system Only one of the two 74377 chips can READ from data bus at a time,

14. ELEC 256 / Saif Zahir UBC / 2000 Registers with Output Enables CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 Q7 Q6 Q5 Q4 D7 D6 D5 D4 \OE Tri-State Buffers CLK D C B A 374 QD QC QB QA QH QG QF QE H G F E OE The 74374 8-bit register has tri-stated outputs, which are enabled by the OE input OE QAQA QHQH QAQA QHQH System Clock 2:1 0 MUX 1 Select Data Bus 74374 Input Data Potential use of 374 packages in a computer system Only one of the two 74374 chips can WRITE to data bus at a time.

15. ELEC 256 / Saif Zahir UBC / 2000 Shift Registers Correct Operation, assuming positive edge triggered FF 4-Bit Shift-register FF0 FF1 IN CLK Q0 Q3 DQDQ Q1 DQ Q2 DQ FF2FF3 Serial input Serial output IN Clk 100 Q0Q0 Q1Q1 Q2Q2 Q3Q3

16. ELEC 256 / Saif Zahir UBC / 2000 Shift Registers J K Q S R J K Q S R J K Q S R J K Q S R + \RESET + Q1Q2Q3Q4 Quad right-shift circular shift register using JK flipflops When RESET=0, Q1 = 1, Q2 = Q3 = Q4 =0 Q1Q2Q3Q4 \RESET = 11000 \RESET = 0, Clk0100 \RESET = 0, Clk0010 \RESET = 0, Clk0001 \RESET = 0, Clk1000 \RESET = 0, Clk0100............... Shift Also called Ring Counter

17. ELEC 256 / Saif Zahir UBC / 2000 Shift-Registers with Parallel Load 0 1 S DQ 0 1 S DQ 0 1 S DQ 0 1 S DQ IN.0IN.1IN.2IN.3 shift/L CLK Q0Q1Q2Q3 2:1 MUX Operation - following positive edges of CLK: if shift/L = 1 --> right-shift function is enabled (Q 0 <-- SI, Q i <-- Q i-1 ) if shift/L = 0 --> parallel-load function is enabled (Q i <-- IN.i ) SI SI = serial input

18. ELEC 256 / Saif Zahir UBC / 2000 Bidirectional Shift-Register Shift 0 1 S DQ 0 1 S DQ 0 1 S DQ 0 1 S DQ Q0Q1Q2 Q4 SLI SRI r/L SRI: serial right inputSLI: serial left input Operation - following positive edges of CLK: if r/L = 1 --> right-shift function is enabled (Q 0 <-- SRI, Q i <-- Q i-1 ) if r/L = 0 --> left-shift function is enabled (Q 4 <-- SLI, Q i <-- Q i+1 )

19. ELEC 256 / Saif Zahir UBC / 2000 Finite State machine (FSM) Design FSMs are sequential machines that can have only a fixed number of states. Counters are FSMs in which the outputs and the states are identical In general the outputs and next states of an FSM are functions of the inputs and present states. The specification of output functions leads to two types of FSMs: –Mealy machines: outputs are functions of inputs and present states –Moore machines: outputs are functions of present states only Combinational logic for outputs and next- states R Inputs X Outputs Z CLK Combinational logic for next-states only R Inputs X Outputs Z Comb. logic for outputs State register Moore Machine Mealy Machine

20. ELEC 256 / Saif Zahir UBC / 2000 Sequential Parity Checker Circuit that counts the 1’s in a bit-serial input stream. Odd-parity circuit: asserts its output when input stream contains an odd number of 1’s Even-parity circuit: asserts its output when input stream contains an even number of 1’s Odd-parity sequential machine Even [0] Odd [1] Reset 1 1 0 0 D C S R Q Q 0 1 Q Clk RESET IN + PS inputNSOutput 0000 0110 1011 1101 State-transition table Realization using a D-FF (a single T-FF can be used instead) CLK = 1 2 3 4 5 6 7 8 9 10 IN = 0 1 0 1 1 0 0 1 1 0 OUT = 0 0 1 1 0 1 1 1 0 1 Example of input/ouput streams NS = PS xor IN OUT = PS

21. ELEC 256 / Saif Zahir UBC / 2000 Finite State machine Design Design Procedure –Understand problem »input-output behavior »define states –Obtain an abstract representation of the FSM »state diagrams, state tables –Perform state minimization –Perform state assignment:In an FSM with N=2 n states, n state variables are needed to encode each state (i.e. each state is encoded by n bits) –Choose flipflop types to implement the FSM: use flipflop excitation tables to derive the flipflop input equations. »JK flipflops tend to reduce gate-count »D flipflops tend to simplify design process –Implement the FSM: use K-maps or Boolean logic to simplify next-state (or flipflop input) equations; simplify output equations

22. ELEC 256 / Saif Zahir UBC / 2000 A Simple Vending Machine Problem Statement: Vending machine delivers a package of gum after receiving 15 cents in coins Machine has a single coin slot and accepts nickels (N) and dimes only (D) Machine does not give back change; inserting 2 dimes returns one package only Vending machine controller design RESET CLK N Vending Machine FSM D OPEN Coin Sensor Package Release Mechanism FSM must remember the total amount that has been received, and release a gum package when 15 cents (or 20) have been received. The machine sensor will reject any unknown coins

23. ELEC 256 / Saif Zahir UBC / 2000 A Simple Vending Machine Constructing a state-diagram Possible states S0: initial (0 cents) state S1: received 5 cents S2: received 10 cents S3: received 15+ cents S0 [0 ¢] S1 [5 ¢] S2 [10¢] S3 [15¢] N N N,D D D Reset State-Encoding: The 4 states of the machine must be encoded in binary. Since we have four states, we need two bits to encode each state (each bit is called a state-variable) Possible encodings StateQ1 Q0 S0 0 0 S1 0 1 S2 1 0 S3 1 1 StateQ1 Q0 S0 0 1 S1 1 1 S2 1 0 S3 0 0

24. ELEC 256 / Saif Zahir UBC / 2000 A Simple Vending Machine PS inputs NS outputs Q1 Q0 D N Q1 + Q0 + OPEN 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 1 1 X X X 0 1 0 0 0 1 0 0 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 1 X X X 1 0 0 0 1 0 0 1 0 0 1 1 1 0 1 0 1 0 1 1 0 1 0 1 1 X X X 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 X X X D-FF implementation D1= Q1 +, D0= Q0 + Q1Q0 DN Q1 D N 0011 0111 XXXX 1111 Q1Q0 DN Q1 D N 0110 1011 XXXX 0111 Q1Q0 DN Q1 D N 0010 0010 XXXX 0010 K-Map for D1K-Map for D0 K-Map for OPEN d1 = q 1 + d + nq 0 d0 = nq 1 + nQ 0 + Nq 0 + dq 1 open = q 1 + q 0

25. ELEC 256 / Saif Zahir UBC / 2000 Vending Machine FSM Implementation DQ DQ CLK \RESET OPEN Q0 Q1 Q0 \Q0 Q0 Q1 N N N N D D D1 D0 d1 = q 1 + d + nq 0 d0 = nq 1 + nQ 0 + Nq 0 + dq 1 open = q 1 + q 0 Flipflop (next-state) equationsFSM Implementation with D flipflops (Moore machine)

26. ELEC 256 / Saif Zahir UBC / 2000 FSM Design for a Vending Machine JK-FF Implementation PS inputs NS FF outputs Q 1 Q 0 D N Q 1 + Q 0 + J 1 K 1 J 0 K 0 OPEN 0 0 0 0 0 0 0 X 0 X0 0 0 0 1 0 1 0 X 1 X0 0 0 1 0 1 0 1 X 0 X0 0 0 1 1 X X X X X XX 0 1 0 0 0 1 0 X X 00 0 1 0 1 1 0 1 X X 10 0 1 1 0 1 1 1 X X 00 0 1 1 1 X X X X X XX 1 0 0 0 1 0 X 0 0 X0 1 0 0 1 1 1 X 0 1 X0 1 0 1 0 1 1 X 0 1 X0 1 0 1 1 X X X X X XX 1 1 0 0 1 1 X 0 0 01 1 1 0 1 1 1 X 0 0 01 1 1 1 0 1 1 X 0 0 01 1 1 1 1 X X X X X XX j1 = d + nq 0 k1 = 0 j0 = nQ 0 + dq 1 k0 = nQ 1 open = q 1 + q 0

27. ELEC 256 / Saif Zahir UBC / 2000 Vending Machine FSM Implementation JQ Q CLK \RESET OPEN Q0 Q1 D Q0 \Q0 Q1 N N D K J K \Q1 N 0 j1 = d + nq 0 k1 = 0 j0 = nQ 0 + dq 1 k0 = nQ 1 open = q 1 + q 0 FSM implementation with JK flipflops (Moore Machine)

28. ELEC 256 / Saif Zahir UBC / 2000 Moore and Mealy Machines: State Diagrams Complete Moore machine state diagram for vending machine Outputs are associated with states (graph nodes) S0 [0] S1 [0] S2 [0] S3 [1] N N N,D D D Reset ND/0 ND Reset OPEN S0 S1 S2 S3 N/0 D/0 D/1 Reset/0 N/0 D/1 N/1 Reset/0 ND/0 Reset/0 Reset/1 OPEN Complete Mealy machine state diagram for vending machine Outputs are associated with inputs along transition arcs

29. ELEC 256 / Saif Zahir UBC / 2000 Moore and Mealy Machines: State Tables PS inputs NS outputs Q1 Q0 D N Q1 + Q0 + OPEN 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 1 1 X X X 0 1 0 0 0 1 0 0 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 1 X X X 1 0 0 0 1 0 0 1 0 0 1 1 1 0 1 0 1 0 1 1 0 1 0 1 1 X X X 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 X X X PS inputs NS outputs Q1 Q0 D N Q1 + Q0 + OPEN 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 1 1 X X X 0 1 0 0 0 1 0 0 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 1 X X X 1 0 0 0 1 0 0 1 0 0 1 1 1 1 1 0 1 0 1 1 1 1 0 1 1 X X X 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 X X X Moore machine state table Outputs are associated with states (graph nodes) S0 S1 S2 S3 S0 S1 S2 S3 Mealy machine state table Outputs are change with inputs Vending Machine Example

30. ELEC 256 / Saif Zahir UBC / 2000 Binary string Recognizers Example: Construct an FSM that receives a bit-serial binary input W and asserts its output Z whenever its input string has at least two 1’s in sequence. Solution: (1,a) - Input-output behavior CLK1 2 3 4 5 6 7 8 9 A B C D W0 1 0 1 1 1 0 1 1 1 1 0 0 Z0 0 0 0 1 1 0 0 1 1 1 0 0 (1.b) - Define states (Moore model) S0: received 0 (most recently)Z=0 S1: received 1 (most recently)Z=0 S2: received two 1’s in sequenceZ=1 (2) - State diagram (Moore model) W=01 11 0 S0 (Z=0) S1 (0) S2 (1) 0

31. ELEC 256 / Saif Zahir UBC / 2000 Binary string Recognizers Example: Binary string recognizer (3) - State assignment: 3 states means that we need two bits to represent each state d1 = wq0 d0 = wq0 + wQ1 z = q1 StateQ1 Q0 S0 0 0 S1 0 1 S2 1 1 DQ DQ CLK Q0 Q1 W D1 D0 R R Z CLK PS IN NS OUT FF Q1 Q0 W Q1+ Q0+ Z D1 D0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 0 0 x x x x x 1 0 1 x x x x x 1 1 0 0 0 1 0 0 1 1 1 1

32. ELEC 256 / Saif Zahir UBC / 2000 Binary string Recognizers Example: Binary string recognizer (1.b) - Define states (Mealy model) S0: received 0 (most recently) S1: received at least one 1 (most recently) (2) - State diagram (Mealy model) (3) - State assignment (S0 := 0, S1 := 1) W=0/Z=0 1/1 1/0 0/0 S0S1 PS IN NS OUT Q W Q+ Z D T J K 0 0 0 0 0 0 0 X 0 1 1 0 1 1 1 X 1 0 0 0 0 1 X 1 1 1 1 1 1 0 X 0 Output Z=WQ D-FF:D=W T-FF:T=W xor Q JK-FF:J=WK= W DQ CLK \RESET W Z

33. ELEC 256 / Saif Zahir UBC / 2000 Analysis of FSMs Problem Given the hardware schematic of a sequential machine, determine its state behavior and output functions. Example: Analyze the following sequential circuit Solution: 1- Find JK input equations 2- Compute next-state equations JQ Q CLK \RESET Z=B A \B X K J K \A X X X a+ = j a A + K a a = xA + (X+b)a b+ = j b B + K b b = xB + (XA+Xa)b j a = xk a = xB j b = xk b = x A z = b AB X 00011110 0 1 0011 1110 K-map for A+ AB X 00011110 0 1 0010 1101 K-map for B+

34. ELEC 256 / Saif Zahir UBC / 2000 FSM Analysis AB X 00011110 0 1 0011 1110 K-map for A+ AB X 00011110 0 1 0010 1101 K-map for B+ A B X A+ B+ Z (=B) 0 0 0 0 0 1 1 1 0 0 1 0 0 0 1 0 1 1 1 1 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 1 1 0 1 S0 S1 S2 S3 More Machine: output isf function of present state only, Z=B S0 Z=0 S1 Z=1 S2 Z=0 X=1 S3 Z=1 X=0 0 0 1 1 0 1

35. ELEC 256 / Saif Zahir UBC / 2000 Sequential (Bit-Serial) Adder Design Sequential adder operation to add two numbers A=a k a k-1... a 1 a 0 and B=b k b k-1... b 1 b 0 - start by adding a 0 and a 0 - output sum bit s 0 and store carry bit c 0 so that it is added to bits a 1 and b 1 in the next clock cycle - repeat the procedure for bits a i and b i (output s i and store carry bit c i ) Direct Design Implement design using a combinational logic block that generates next-state and output functions, and a storage element (D-FF) to store present state D C S R Q Q A B Z 1 CLK \CLR Clock cycle 4 3 2 1 1 0 0 1 0 1 1 1 1 0 SUM 0 0 0 1 0 0 1 0 C Present state Next state LSB Mealy Model

36. ELEC 256 / Saif Zahir UBC / 2000 Sequential Adder Design using Formal Methods Inputs: A, BOutput: Z=SUM States (last carry bit): S0: carry was 0 S1: carry was 1 AB=11/Z=0 01/0 10/0 11/1 00/0 01/1 10/1 00/1 S0S1 PS IN NS OUT FF Q A B Q+ Z D J K 0 0 0 0 0 0 0 x 0 0 1 0 1 0 0 x 0 1 0 0 1 0 0 x 0 1 1 1 0 0 1 x 1 0 0 0 1 1 x 1 1 0 1 1 0 1 x 0 1 1 0 1 0 1 x 0 1 1 1 1 1 1 x 0 RESET j = ab k = AB AB Q 00011110 0 1 0010 XXXX K-map for J AB Q 00011110 0 1 XXXX 1000 K-map for K Z = A xor B xor Q D= Q

37. ELEC 256 / Saif Zahir UBC / 2000 Moore Machine Realization of Sequential Adder More states are required for Moore Model S0: C=0 and Z=0 (C=carry, Z:sum) S1: C=0 and Z=1 S2: C=1 and Z=0 S3: C=1 and Z=1 S0 Z=0 S2 Z=0 RESET S0 Z=0 S2 Z=0 00 11 00 11 00 01 10 01 10 00 01 10 01 10 Two flipflops are needed to implement the Moore Model sequential adder Ex.: Implement this state diagram using D, flipflops and JK flipflops State Diagram