1. October 11, 20001

2. 2 Platform Design Considerations Jim Choate Intel Corporation

3. October 11, 20003 Agenda w Guidelines w Measurement Techniques w Testing Results w Summary

4. October 11, 20004 Guidelines w USB 2.0 guidelines are more systematic, detailed than 1.x whitepapers w The USB 2.0 Platform Design Guideline, Revision 0.9 is available now – http://developer.intel.com/technology/usb/techlit.htm w Guideline areas: – Board routing, placement and layout guidelines – EMI/EMC solutions – Front panel USB design guidelines

5. October 11, 20005 Proposed Guidelines w USB 2.0 Peripheral Design Guideline w Other Proposed Guideline Areas: – TDR Testing – Oscilloscope Setups u CHIRP Testing u Device Signal Quality Testing u Host Signal Quality Testing – Test Fixture Design And Usage – Hub Repeater Testing

6. October 11, 20006 Board Design w 4 layer sufficient; trace impedance matching is key w 3 ns + 26 ns + 1 ns w Maximum Motherboard Trace Length Of 18 Inches – Cable + Traces  18 Inches For Front Panel Solutions w Do not cross plane splits w Minimize vias w Maximize distance to other traces Motherboard Is the Toughest Environment

7. October 11, 20007 Board Design Guidelines w Board Stack-up: – 4 layer, impedance controlled boards required – Impedance targets must be specified – Ask your board vendor what they can achieve Classic four-layer stack Signal 1 Prepreg VCC Core Ground Prepreg Signal 2 Example target impedance: 0.005 in trace at 60+/-15%  7.5mil traces with 7.5mil spacing Zdiff  90 

8. October 11, 20008May 17, 20007 Routing Guidelines w Control trace widths to obtain target impedance – Ask your board vendor what they can achieve – As always, cost is a consideration w Maintain strict trace spacing control w Minimize stubs D-D- D+D+ 15k  Correct way to connect to resistors

9. October 11, 20009 Routing Guidelines w Routing over plane splits w Creating stubs with test points w Violating trace spacing guidelines Common Routing Mistakes Ground or power plane tp Don’t cross plane splits Proper routing technique maintains spacing guidelines

10. October 11, 200010 Motherboard Front Panel Daughter Card Board Design w Daughtercard at front/side panel – Bypass caps, EMI control components, strain relief w Header and cable – Keyed header, cable of limited length and matched impedance Front/Side Panel Connectors

11. October 11, 200011May 17, 20009 Measurement Techniques w Selecting Appropriate Test Equipment – Accurate measurement of signal quality requires an oscope and probes with adequate BW and sample rate – Proper test fixtures are also important Equipment that will work Scope: TDS 694C - 10GS/s, 3Ghz Probe: P6247 Fet Probe - 4Ghz,.4pF typ 90  Differential Probe

12. October 11, 200012 Board Testing w Use TDRs To Verify Adherence To Budget – Typical TDR measurement u Refer to section 7.1.6.2 of the specification for details

13. October 11, 200013 Board Testing w USB 2.0 test mode software will be used to enable device and host controller tests w USB 2.0 test fixture will be used to provide ideal termination for signal quality measurement w Differential signaling requires the use of a differential probe HS Relay Differential Probe Test Mode SW USB 2.0 test fixture HS Device Oscilloscope

14. October 11, 200014 EMI w USB1.X EMI solutions don’t work for USB2 – Low pass filters damage USB 2.0 HS signal quality D+ D - Vcc USB A Connector Typical USB 1.1 Termination Scheme

15. October 11, 200015 EMI w Common mode chokes are a proven USB 2.0 EMI solution – Refer to the USB 2.0 Design Guideline for solutions that work for USB 2.0 FS & HS signal quality requirements

16. October 11, 200016 EMI w Proper grounding of chassis is crucial – Connector shell must connect to green wire ground early and well – IO shield must connect securely to chassis and receptacle w 2 wire common mode choke is preferred – Blocks common mode EMI from leaving chassis – Common mode impedance @ 100 Mhz should be < 300 Ohms – Differential Impedance @ 100 Mhz should be < 8 Ohms

17. October 11, 200017 ESD, EMC w ESD strikes spread out in time by inductance of cables and hubs in series – Bypass/flyback caps on Vbus near connector help w Hardware Protection – Well-grounded shield – Common mode choke – Spark gap arrestors – Shielded cables

18. October 11, 200018 DP1 DM1 1.51.551.61.651.71.751.81.851.9 x 10 -5 0 0.5 1 1.5 2 2.5 3 3.5 s V keyboard glitch ESD, EMC w Differential squelch/disconnect w Pattern matching before connectivity w Sampling over extended times e.g. Chirp w Low speed requires cables with at least a foil shield Noise Immunity Built Into Low-Level Protocol

19. October 11, 200019 USB2 Validation Motherboard Front Panel Test Chip Back Panel Test Chip Early Testing Results

20. October 11, 200020 Routing Paths Tested USB Connector Motherboard PCI SLOT LAN South Bridge NECtest chip chip Long Route Front Panel Header Early Testing Results Motherboard PCI SLOT LAN South Bridge USB Connector Short Route NEC test chip

21. October 11, 200021 TP2TP3 Early Testing Results w Back Panel Eye Pattern Results – EMI/ESD components – Both at A-connector (TP2) and at end of USB cable (TP3) – Three-stack connector on MB

22. October 11, 200022 18” Shielded, twisted pair 18” ribbon cable Early Testing Results w Front Panel Header Cable Options Tested

23. October 11, 200023 Shielded Front Panel Cable Ribbon Front Panel Cable Early Testing Results w Front-panel Cable Implementation Eye Pattern Results – 18 inch, twisted pair, shielded front panel cable – 18 inch unshielded front panel “ribbon” cable

24. October 11, 200024 Early Testing Results w Front-panel Cable Implementation Eye Pattern Results – 18 inch, twisted pair, shielded front panel cable – 18 inch unshielded front panel “ribbon” cable Connector reference 80  72  110  1.4 ns exception window Shielded, Twisted Pair Front Panel Cable 114  145  114  Ribbon Front Panel Cable Connector reference

25. October 11, 200025 Recent Testing Results w Back Panel Eye Pattern Results – EMI/ESD components – At the A-connector (TP2)

26. October 11, 200026May 17, 200017 Host turns on HS termination Reset Recent Testing Results w CHIRP Testing – Measured with single ended probes – At the A-connector (TP2) w Important Parameters – Reset duration – CHIRP K amplitude – CHIRP K duration – HS termination timing – Host CHIRP amplitude

27. October 11, 200027May 17, 200022 Summary w USB 2.0 Design Presents New Challenges – Board layout – Common mode chokes – Front Panel Solutions – Signal Quality Measurement – Compliance Testing w USBIF Is Providing Design Guides In Such Areas