1. A 0.35μm CMOS Comparator Circuit For High-Speed ADC Applications Samad Sheikhaei, Shahriar Mirabbasi, and Andre Ivanov Department of Electrical and Computer Engineering University of British Columbia 2356 Main Mall, Vancouver, BC, V6T 1Z4, Canada  系所：積體電路設計研究所  學生：劉得吉  學號： 95662001

2. O utLine  Abstract  Introduction  Comparator architecture  Layout of the circuit and a Micrograph  Test setup of the Chip  Conclusions  Refernces

3. A bstract  The comparator consists of a preamplifier and a latch stage and an output sampler.  The output sampler circuit consists of a full transmission gate (TG) and two inverters.  Measurement results show a sampling frequency of 1GHz with 16mV resolution for a 1V input signal range and 2mW power consumption from a 3.3V.

4. I ntroduction  High-speed comparators are essential building blocks in high-speed flash analog- to-digital converters.  Comparator ： a preamplifier, a latch and an output sampler.  The last latching stage usually consumes a significant power.  Typically problematic charge injection phenomenon of the transistors in the transmission gate.

5. Ciruct blocks of the proposed comparator A Preamplifier A Latch A Output samplers

6. P reamplifier circuit

7. Latch and Output sampler circuit

8. Sampling clock generators circuit

9. T.G Circuit

10. L ayout of the circuit and a M icrograph

11. T est setup of the C hip

12. MEASUREMENT RESULTS

13. R efernces  Choi, Abidi, “ A 6b 1.3Gsample/s A/D converter in 0.35 µ m CMOS ”,IEEE J. Solid-State Circuits, vol. 36, pp. 1847 – 1858, Dec. 2001.  Mehr, Dalton, “ A 500-MSample/s, 6-b nyquist-rate ADC for diskdrive read-channel application ”, IEEE J. Solid-State Circuits, vol. 34,pp. 912 -920, July 1999.  D. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley, 1997.  C. Donovan and M. P. Flynn, “ A ‘ digital ’ 6-bit ADC in 0.25 µ m CMOS, ” IEEE J. Solid-State Circuits, vol. 37, pp. 432-437, March ， 2002.