1. Phase Locked Loop Design KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering CSE598A/EE597G Spring 2006

2. Frequency Synthesizer

3. General Synthesizer Issues

4. Frequency Spectrum

5. Settling Time (Lock Time)

6. PLL Components Circuits

8. Reference Circuit

9. PLL Components Circuits

10. PFD and Charge Pump Spur!!

11. Phase Frequency Detector(1)

12. Phase Frequency Detector(2)

13. PFD and modified flip-flop B.park, “A 1GHz, Low-Phase-Noise CMOS Frequency Synthesizer with Integrate LC VCO for Wireless Communications“, CICC 1998 Park, Byungha? GIT PhD. Samsung LSI, RF/Analog IC Group

14. New Modified flip-flop by KT Reduce signal path High speed 10 Transistors Negative reset No oscillation Customized

15. D Flip-Flop

16. DFF Simulation Comparison Modifed FF by KT DFF

17. PFD Simulation(1)

18. PFD Simulation(2)

19. PFD Simulation(3)

20. PFD Output Stage-Charge Pump Programmable

21. Charge Pump (Drain–s/w) My first Charge pump. Easy to design and understand how to work Spike Noise from net76 when U2 turn on High noise contribution! If you designed CP like this, you got fired!

22. Charge Pump (Source-s/w) Low charge sharing Low noise Suppression the Spur Level? Why? Cascode? >High impedence >Pole!!!

23. Charge Pump Simulation CP_Drain CP_Source V(U/D) I(U) I(D)

24. Charge Pumps  Rhee, W., "Design of high performance CMOS charge pumps in phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548  J. S. Lee, M. S. Keel, S. I. Lim, and S. Kim, “Charge pump with perfect current matching characteristics in phase-locked loops,” Electronics Letters, Vol. 36, No. 23, pp. 1907-1908, November 2000.

25. Loop Filter(1)

26. Loop Filter(2)

27. PLL Components Circuits

28. Differential Delay Cell-Single pass Chan-Hong Park, Solid-State Circuits, 1999.

29. Differential Delay Cell-Multiple pass Yalcin Alper Eken, Solid-State Circuits, 2004 Negative Skewed Delay Scheme: Seog-Jun, Lee, ISSC, 1997

30. Single pass Ring OSC.

31. Multiple pass Ring OSC. Which one is faster? 1.3 stage single pass Ring OSC. 2.5 stage multiple pass Ring OSC.

32. 3 Stage-Single pass Ring OSC. 220MHz~825MHz @ V(Ctrl)=1.65V~3.3V

33. 3 Stage-Single pass Ring OSC.

34. 5 Stage-Multiple pass Ring OSC. 1.65GHz~2.5GHz @ V(Ctrl) 1.65V~3.3V

35. How to simulate Oscillator in Hspice? .Option  Transient Step  Start-up time  Triggered Signal  Frequency Measure Tool: Cscope

36. PLL Components Circuits

37. Frequency Divider Input stage-high speed, low power, Following stages-High speed Differential type-Suppression Noise Input buffer is required

38. N=64 Divider Simulation

39. Input buffer

40. PLL Simulation V(VCO) V(Ref) V(DiV) V(Up) V(Dn) V(Ctrl)