1. The ARM Programmer’s Model
Jacob Huerta, Ryan Crell, and Veronica Hohe
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2. Outline ARM Registers Von Neumann Cycle Sequence CPSR Memory
Standard ARM vs. Thumb ARM Instructions
ARM Instructions
Supervisor Mode/Kernel Mode
Exceptions
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3. ARM Registers
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4. ARM Registers Instruction set = operations to change system state
State = data items in processor’s visible registers/systems memory
Multiple invisible registers in a processor
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5. ARM Registers User-level programming
15 general purpose registers PC
CPSR
System-level programming/exceptions
Remaining registers
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6. Von Neumann Cycle Sequence
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7. Von Neumann Cycle Sequence
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8. CPSR
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9. ARM CPSR Control Bits Protected from user-level programs Mode T IF
Control the processor mode
Bits 0-4 (must be a valid mode) T
Control the instruction set
State bit IF
Enables control interrupt
Bit 6 is FIQ disable and Bit 7 is IRQ disable
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10. ARM CPSR Flag Bits Condition Code Flags NZCV N (“Negative flag”)
0/1 = value is positive/negative
Z (“Zero flag”)
0/1 = result is non-zero/zero
C (“Carry flag”)
0/1 = “extends” for shift/”borrows” for subtraction
V (“Overflow flag”)
0/1 = no overflow/overflow caused by last arithmetic operation
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11. ARM CPSR Unused Bits Unused bits Reserved
State preserved when changing the flag or control bits
Should not be altered by programs
Should not rely on them when checking the PSR status
Might read as 1’s or 0’s in future processors
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12. ARM Memory Organization
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13. ARM Memory Organization
View memory as linear array of bytes numbered from 0 to 232-1
Store data items in
Byte (8 bits)
Half-word (16 bits)
Word (32 bits)
Align words on 4 bytes
Organize in little-endian style
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14. ARM Instructions
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15. ARM vs. THUMB Instructions
32-bit instruction set
3-data address instructions
16 general purpose registers
16-bit instruction set
2-data address instructions
8 general purpose registers
“Less regular” instructions
Higher code density
High performance
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16. ARM vs. THUMB Instructions
Not a “complete” architecture
Supports ARM architecture
The T bit in CPSR toggles the interpretation
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17. ARM vs. THUMB Instructions
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18. ARM Instructions Load-store architecture
Processes only values stored in registers and instructions
Performs operations on these values
Stores results in register
Affects memory using only load and store instructions
Inability to perform memory-to-memory operations
Instructions
Data processing: between registers (add, sub, etc.)
Data transfer: between registers and memory (load, store)
Control flow: execution of instructions (branches, link, supervisor calls)
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19. Supervisor Mode/Kernel Mode
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20. Supervisor Mode/Kernel Mode
User with supervisor privileges can use system calls to affect
Kernel code
Device drivers
Privileged code
User program with IO access permissions
Unprivileged code
User programs
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21. Exceptions
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22. Exceptions Normal execution is paused to handle events like
Systems calls
Interrupts generated by external sources
Undefined instructions
Traps
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23. Exception Handling Save current state is
Copy PC into register rl4_exc
Copy CPSR into register SPSR_exc
Register r13_exc = pointer to memory stack to store user registers
Set processor operating mode to exception mode
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24. Exception Handling
Set PC to value between 0x00 and 0x1C depending on exception type
Restore user registers from memory stack
Restore (adjusted) PC and CPSR
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25. Input/Output (I/O) System
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26. Input/Output (I/O) System
I/O peripheral
Device mapped to memory
Device registers treated as memory locations by system
Given interrupt support (make interrupt requests)
Normal interrupt (IRQ) = most requests
Fast interrupt (FIQ) = time-sensitive/critical requests
Direct Memory Access (DMA)
External to ARM processor
Handles high-bandwidth I/O traffic
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27. References
(2001). “The Thumb Instruction Set.” Web January 28, 2015.
(2014). “About processor exceptions.” ARM. Web.
(2014). “Exception handling process.” ARM. Web.
(2014). “Load/store architecture.” Wikipedia. Web. August 4,
(2014). “Protection ring.” Wikipedia. Web. December 30,
(2014). “Reserved bits.” ARM. Web. August 4,
(2014). “Trap (computing).” Wikipedia. Web. April 30,
Furber, S. (2000). ARM system-on-chip architecture. Harlow, England: Addison-Wesley. (2014).
Gibson, J. (2011). ARM assembly language: An Introduction (2nd ed.). Lexington, KY: The Author.
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28. Questions?
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