1. MICROCONTROLLER INSTRUCTION SET
Subject: MICROCONTROLLER AND EMBEDED SYSTEM Class: 5th, ECE PRESENTED BY MANJIT SINGH BHULLAR SR. LECTURER, GPC BATHINDA. Mobile No.:
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2. Introduction
An instruction is an order or command given to a processor by a computer program. All commands are known as instruction set and set of instructions is known as program.
8051 have in total 111 instructions, i.e. 111 different words available for program writing.
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3. Instruction Format
Where first part describes WHAT should be done, while other explains HOW to do it.
The latter part can be a data (binary number) or the address at which the data is stored.
Depending upon the number of bytes required to represent 1 instruction completely.
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4. Types Of Instructions Instructions are divided into 3 types;
One/single byte instruction.
Two/double byte instruction.
Three/triple byte instruction.
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5. Types Of Instructions One/single byte instructions :
If operand is not given in the instruction or there is no digits present with instruction, the instructions can be completely represented in one byte opcode.
OPCODE bit
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6. Types Of Instructions Two/double byte instruction:
If 8 bit number is given as operand in the instruction, the such instructions can be completed represented in two bytes.
First byte OPCODE
Second byte bit data or I/O port
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7. Types Of Instructions 3. Three/triple byte instruction:
If 16 bit number is given as operand in the instructions than such instructions can be completely represented in three bytes 16 bit number specified may be data or address.
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8. Types Of Instructions 1. First byte will be instruction code.
2. Second byte will be 8 LSB’s of 16 bit number.
3. Third byte will be 8 MSB’s of 16 bit number.
First byte OPCODE.
Second byte LSB’s of data/address.
Third byte MSB’S of data/address.
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9. Addressing Modes
Addressing modes specifies where the data (operand) is. They specify the source or destination of data (operand) in several different ways, depending upon the situation.
Addressing modes are used to know where the operand located is.
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10. Addressing Modes There are 5 types of addressing modes:
Register addressing.
Direct addressing.
Register indirect addressing.
Immediate addressing.
Index addressing.
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11. Register Addressing Mode
In register addressing mode; the source and/or destination is a register.
In this case; data is placed in any of the 8 registers(R0-R7); in instructions it is specified with letter Rn (where N indicates 0 to 7).
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12. Register Addressing Mode
For example;
ADD A, Rn (This is general instruction).
ADD A, R5 (This instruction will add the contents of register R5 with the accumulator contents).
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13. Direct Addressing Mode
In direct addressing mode; the address of memory location containing data to be read is specified in instruction.
In this case; address of the data is given with the instruction itself.
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14. Direct Addressing Mode
For example;
MOV A, 25H (This instruction will read/move the data from internal RAM address 25H and store it in the accumulator.
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15. Register Indirect Addressing Mode
In register indirect addressing mode; the contents of the designated register are used as a pointer to memory.
In this case; data is placed in memory, but address of memory location is not given directly with instruction.
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16. Register Indirect Addressing Mode
For example;
MOV This instruction moves the data from the register whose address is in the R0 register into the accumulator.
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17. Immediate Addressing Mode
In immediate addressing mode, the data is given with the instruction itself.
In this case; the data to be stored in memory immediately follows the opcode.
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18. Immediate Addressing Mode
For example;
MOV A, #25H (This instruction will move the data 25H to accumulator.
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19. Index Addressing Mode
Offset (from accumulator) is added to the base index register( DPTR OR Program Counter) to form the effective address of the memory location.
In this case; this mode is made for reading tables in the program memory.
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20. Index Addressing Mode For example;
MOVC A + DPTR ( This instruction moves the data from the memory to accumulator; whose address is computed by adding the contents of accumulator and DPTR)
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21. Types Of Instructions Data transfer instructions.
Arithmetic instructions.
Logical instructions.
Logical instructions with bits.
Branch instructions.
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22. Data Transfer Instructions
These instructions move the content of one register to another one.
Data can be transferred to stack with the help of PUSH and POP instructions.
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23. Data Transfer Instructions
MNEMONIC DESCRIPTION BYTES
MOV A,Rn (A) (Rn)
MOV A,Rx (A) (Rx)
MOV (A) (Ri)
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24. Data Transfer Instructions
MOV A,#X (A) Data
MOV Rn,A (Rn) (A)
MOV Rn, Rx (Rn) (Rx)
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25. Data Transfer Instructions
MOV Rn, #X (Rn) Data
MOV Rx, A (Rx) (A)
MOV Rx, Rn (Rx) (Rn)
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26. Data Transfer Instructions
MOV Rx, Ry (RX) (Ry)
MOV Ri (Rx) (Ri)
MOV Rx, # X (Rx) Data
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27. Data Transfer Instructions
Ri, A (Ri) (A)
Ri, Rx (Ri) (Rx)
Ri, #X (Ri) Data
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28. Data Transfer Instructions
MOV DPTR, #X (DPTR) Data
MOVC (A) (A+DPTR) A+DPTR
MOVC (A) (A+PC)
A+PC
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29. Data Transfer Instructions
MOVX Ri A (Ri)
MOVX (A) (DPTR)
A (Ri) (A)
DPTR
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30. Data Transfer Instructions
(DPTR) (A)
PUSH Rx Push directly addressed Rx register on stack
POP Rx (A) (Rx)
DPTR, A
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31. Data Transfer Instructions
XCH A, Rn (A) (Rn)
XCH A, Rx (A) (Rx)
XCH (A) (Ri)
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32. Data Transfer Instructions
XCHD Exchange 4 lower bits in accumulator with indirectly addressed register
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33. Arithmetic Instructions
These instructions perform several basic operations. After execution, the result is stored in the first operand.
8 bit addition, subtraction, multiplication, increment-decrement instructions can be performed.
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34. Arithmetic Instructions
MNEMONICS DESCRIPTION BYTE
ADD A, Rn A = A + Rn
ADD A, Rx A = A + Rx
AAD Ri A = A+ Ri
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35. Arithmetic Instructions
ADD A, # X A = A + Byte
ADDC A, Rn A = A + Rn + C
ADDC A , Rx A = A + Rx + C
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36. Arithmetic Instructions
ADDC Ri A = A + Ri + C
ADDC A, # X A = A + Byte + C 2
SUBB A, Rn A = A – Rn –
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37. Arithmetic Instructions
SUBB A, Rx A = A – Rx –
SUBB Ri A = A – Ri –
SUBB A, # X A = A – Byte –
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38. Arithmetic Instructions
INC A A = A
INC Rn Rn = Rn
INC Rx Rx = Rx
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39. Arithmetic Instructions
Ri Ri = Ri
DEC A A = A –
DEC Rn Rn = Rn –
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40. Arithmetic Instructions
DEC Rx Rx = Rx –
Ri Ri = Ri –
INC DPTR DPTR = DPTR
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41. Arithmetic Instructions
MUL AB B:A = A * B
DIV AB A = [A/B]
DA A Decimal adjustment of accumulator according to BCD code
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42. Logical Instructions
These instructions perform logical operations between two register contents on bit by bit basis.
After execution, the result is stored in the first operand.
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43. Logical Instructions MNEMONIC DESCRIPTION BYTE
ANL A, Rn (A) (A) ^ (Rn)
ANL A, Rx (A) (A) ^ (Rx)
ANL Ri (A) (A) ^ (Ri)
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44. Logical Instructions ANL A, # X (A) (8 bit data) ^ (A) 2
ANL Rx, A (Rx) (A) ^ (Rx)
ANL Rx,# X (Rx) (8 bit data) ^ (Rx)
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45. Logical Instructions ORL A, Rn (A) (A) + (Rn) 1
ORL A, Rx (A) (A) + (Rx)
ORL Ri (A) (A) + (Ri)
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46. Logical Instructions ORL Rx, A (Rx) (A) + (Rx) 2
ORL Rx,# X (Rx) (8 bit data) + (Rx) 2
XORL A, Rn Logical exclusive OR operation between the contents of accumulator and R register.
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47. Logical Instructions XORL A, Rx Logical exclusive OR 2
operation between the contents of the accumulator and directly addressed register Rx.
XORL Ri Logical exclusive OR operation between the contents of the accumulator and directly addressed register.
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48. Logical Instructions
XORL A, # X Logical exclusive OR operation between the contents of accumulator and the given 8 bit data.
XORL Rx, A Logical exclusive OR operation between the contents of the accumulator and directly addressed register Rx.
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49. Logical Instructions
XORL Rx, # X Logical exclusive OR operation between the contents of the directly addressed register Rx and the given 8 bit data.
CLR A (A)
CPL A (A) (/A)
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50. Logical Instructions SWAP A (A3-0) (A7-4) 1 RL A (An + 1) (An) 1
RLC (An + 1) (An)
(A0) ( C )
( C ) (A7)
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51. Logical Instructions RR A (An) (An + 1) 1 (A7) (A0)
RRC A (An) (An + 1)
(A7) ( C )
( C ) (A0)
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52. Logical Instructions On Bits
Similar to logical instructions, these instructions also perform logical operations.
The difference is that these operations are performed on single bits.
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53. Logical Instructions On Bits
MNEMONIC DESCRIPTION BYTE
CLR C ( C = 0 )
CLR bit clear directly addressed bit 2
SETB C ( C = 1 )
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54. Logical Instructions On Bits
SETB bit Set directly addressed bit
CPL C (1 = 0, 0 = 1)
CPL bit Complement directly addressed bit
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55. Logical Instructions On Bits
ANL C, bit Logical AND operation between Carry bit and directly addressed bit.
ANL C,/bit Logical AND operation between Carry bit and inverted directly addressed bit.
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56. Logical Instructions On Bits
ORL C, bit Logical OR operation between Carry bit and directly addressed bit.
ORL C,/bit Logical OR operation between Carry bit and inverted directly addressed bit.
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57. Logical Instructions On Bits
MOV C, bit Move directly addressed bit to carry bit.
MOV bit, C Move Carry bit to directly addressed bit.
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58. Program Flow Control Instructions
In this group, instructions are related to the flow of the program, these are used to control the operation like, JUMP and CALL instructions.
Some instructions are used to introduce delay in the program, to the halt program.
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59. Program Flow Control Instructions
MNEMONIC DESCRIPTION BYTE
ACALL adr (PC) (PC)
(SP) (SP) + 1
((SP)) (PC7 – 0)
((SP)) (PC15-8)
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60. Program Flow Control Instructions
LCALL adr (PC) (PC)
(SP) (SP) + 1
((SP)) (PC7-0)
(SP) (SP) + 1
((SP)) (PC15-8)
(PC) addr15-0
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61. Program Flow Control Instructions
RET (PC15-8) ((SP))
(SP) (SP) – 1
(PC7-0) ((SP))
(SP) (SP) - 1
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62. Program Flow Control Instructions
RET (PC15-8) ((SP))
(SP) (SP) – 1
(PC7-0) ((SP))
(SP) (SP) – 1
AJMP addr (PC) (PC)
(PC10-0) page address
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63. Program Flow Control Instructions
LJMP addr (PC) addr
SJMP rel short jump from
(from -128 to +127 locations in
relation to first next instruction)
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64. Program Flow Control Instructions
JC rel (PC) (PC)
IF ( C ) = 1
THEN (PC) (PC) + rel
JNC rel (PC) (PC)
IF ( C) = 0
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65. Program Flow Control Instructions
JB bit, rel Jump if addressed
bit is set. Short jump.
JBC bit, rel Jump if addressed
bit is set and clear it.
Short jump.
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66. Program Flow Control Instructions
+ DPTR (PC) (A) + (DPTR) 1
JZ rel (PC) (PC)
IF (A) = 0
THEN (PC) (PC) + rel
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67. Program Flow Control Instructions
JNZ rel (PC) (PC)
IF (A) = 0
THEN (PC) (PC) + rel
CJNE A, Rx, rel Compare the contents 3
of acc. And directly addressed register Rx. Jump if they are different. Short jump.
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68. Program Flow Control Instructions
CJNE A, #X, rel (PC) (PC)
IF ( A) < > data
THEN (PC) (PC) + relative
offset
IF (A) < data
THEN ( C )
ELSE ( C )
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69. Program Flow Control Instructions
RI, # x, rel (PC) (PC)
IF (Rn) <> data
THEN (PC) (PC) + relative
offset
IF (Rn) < data
THEN ( C )
ELSE ( C )
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70. Program Flow Control Instructions
Ri, # X, rel (PC) (PC)
IF ((Ri)) <> data
THEN (PC) (PC) + relative
offset
IF ((Ri)) < data
THEN ( C ) 1
ELSE ( C ) 0
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71. Program Flow Control Instructions
DJNZ Rn , rel (PC) (PC)
(Rn) (Rn) - 1
IF (Rn) > 0 or (Rn) < 0
THEN (PC) (PC) + rel
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72. Program Flow Control Instructions
DJNZ Rx, rel (PC) (PC)
(Rx) (Rn) – 1
IF (Rx) > 0 or (Rx) < 0
THEN (PC) (PC) + rel
NOP No operation
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73. Summary Instruction set. Addressing modes. Data transfer instruction.
Arithmetic instruction.
Logical instruction.
Logical operation on bits.
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