1. Interrupts, Phototransistors, Opto-isolators, Triacs, and Thermistors Alex Buchanan Aaron May Peter Ngo

2. Reason for Interrupts You might want a certain subroutine executed immediately after a request from an external device or from an internal program, providing certain conditions are met. Interrupts do just this by suspending the execution of the current program in order to execute the subroutine

3. Request Checking Implementation There are 2 ways of implementing Request Checking Polling Interrupts

4. Polling Polling iteratively checks a device or registers for data. This method of implementing request checking is cumbersome as it requires the MC to frequently suspend operations to check for new data from devices or registers.

5. Interrupts Nothing is done until a Request is issued Once issued, the CPU suspends execution of the main program until instructions in the Interrupt Service Routine (ISR) are executed More efficient than constantly scanning devices or registers for new Data

6. Interrupts: Flow Back to Main Program XI Software Interrupt (SWI) Maskable Wait For Interrupt (WAI) Mask Set Hardware Interrupt Begin Interrupt Program (ISR) Store MPU Registers to SP Condition Code Register Accumulator B Accumulator A Index Register (MS) Index Register (LS) Program Counter (MS) Program Counter (LS) SP SP -1 SP -2 SP -3 SP -4 SP -5 SP -6 Condition Code Register Stack Pointer Load Interrupt Vector into PC Complete Current Instruction Complete Current Instruction 0 1YES NO Set Mask (CCR4) (set to 1) Interrupt Vector Clear Mask (CCR4) (set to 0) Maskable Wait For Interrupt (WAI) Hardware Interrupt Is the Mask Set? NO YES 01 NO

7. Stacking Order when an Interrupt Occurs Memory Location CPU Registers SPPCL SP-1PCH SP-2IYL SP-3IYH SP-4IXL SP-5IXH SP-6ACCA SP-7ACCB SP-8CCR Last value to be pulled from stack

8. Interrupts: Flow: IRQ Example 1 1.If I bit in CCR is not set (I=0) and IRQ goes low for at least 2 cycle, the IRQ sequence is entered. 2.Internal registers  stored to RAM (SP). 3.The IRQ mask bit set (I=1). 4.Data at FFF2 gets loaded into PCH 5.Data at FFF3 gets loaded into PCL 6.PC contents go out on address bus during 1. 7.Contents of the location addressed enter instruction register and are decoded as first instruction of interrupt routine. 8.If it is a more than 1-byte instruction, additional bytes enter MPU for execution. If not, go to next step 9.After execution, step 7 is repeated for subsequent instructions. This is repeated until “RTI” is executed. RTI tells the MPU that service is complete and that it may reload the registers and continue the main program from where it left off. Back to Main Program Software Interrupt (SWI) Maskable Wait For Interrupt (WAI) Mask Set Hardware Interrupt Begin Interrupt Program (ISR) Store MPU Registers to SP Load Interrupt Vector into PC Complete Current Instruction Complete Current Instruction 0 1YES NO Set Mask (CCR4) (set to 1) Clear Mask (CCR4) (set to 0) Maskable Wait For Interrupt (WAI) Hardware Interrupt Mask Set NO YES 01 NO

9. Interrupt Types 2 Types : Maskable 27 Maskable Interrupts Split into Local and Global Types Lower Priority than Non-Maskable Priority between Maskable Interrupts can be adjusted via the HPRIO Non-Maskable 6 Non-Maskable Interrupts Default Priority between Non-Maskable Interrupts that cannot be adjusted

10. Maskable Interrupts Global I-bit in the CCR Local Interrupt enable bit Follows a default priority arrangement Any one interrupt can be promoted to higher priority using HPRIO register 1.IRQ 2.Real-Time Interrupt 3.Standard Timer Channel 0 4.Standard Timer Channel 1 5.Standard Timer Channel 2 6.Standard Timer Channel 3 7.Standard Timer Channel 4 8.Standard Timer Channel 5 9.Standard Timer Channel 6 10.Standard Timer Channel 7 11.Standard Timer Overflow 12.Pulse Accumulator A Overflow 13.Pulse Accumulator Input Edge 14.SPI transfer Complete 15.SCI system 16.ATD 17.Port J 18.CRG PLL Lock 19.CRG Self Clock Mode 20.Flash 21.CAN Wakeup 22.CAN Errors 23.CAN Receive 24.CAN Transmit 25.Port P 26.PWM Emergency Shutdown 27.VREG LVI Any can be assigned the highest maskable interrupt priority...

11. Maskable Interrupts: IRQ Input IRQ pin provides additional external interrupting source IRQE bit in Options Register used to configure IRQ for Edge-Sensitive-Only Operation IRQE = 0  IRQ is configured for low level sensitive operation IRQE = 1  IRQ is configured for falling edge-sensitive operation

12. HPRIO Register for Maskable Interrupts Used to elevate priority of any one maskable interrupt Default is IRQ Set by changing contents of HPRIO (Highest Priority Interrupt Register) Can only be written when I-bit is set

13. HPRIO Register for Maskable Interrupts Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 PSEL7PSEL6PSEL5PSEL4PSEL3PSEL2PSEL1 Address: $001F PSEL[7:1] – Priority Select Bits Selects one interrupts source to be elevated Can only be written while I-bit in the CCR is set Write the low byte of the maskable interrupt vector to HPRIO to elevate that maskable interrupt to the highest priority Ex: writing $DE to HPRIO elevates the Standard Timer Overflow to highest priority (Standard Timer Overflow vector = $FFDE) Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 1101111 PSEL7PSEL6PSEL5PSEL4PSEL3PSEL2PSEL1-

15. Non-Maskable Interrupts 6 Non-Maskable Interrupts Follows a default priority arrangement Interrupts are not subject to global masking Except XIRQ Global mask is X in CCR 1.POR of RESET pin 2.Clock monitor reset 3.COP watchdog reset 4.Unimplemented instruction trap 5.Software interrupt (SWI) 6.XIRQ interrupt

16. Non-Maskable Interrupts: Unimplemented instruction trap Generates interrupt request to Unimplemented instruction trap vector Reinitializes stack pointer once interrupt service is completed Left un-initialized, illegal opcode vector can cause infinite loop causing stack underflow

17. Non-Maskable Interrupts: Software Interrupt-SWI Software instruction, thus cannot be interrupted until completed Uninhibited by global mask bits in the CCR Similar to other interrupts, sets I-bit upon servicing

18. Non-Maskable Interrupts: XIRQ Enabled by TAP (Transfer accumulator A to CCR) which, while being unable to transfer the X-bit from 0->1 will convert the X-bit from 1->0 After it is cleared, software cannot set X-bit (only set by the XIRQ or during Reset), thus XIRQ is non- maskable Higher priority than any source maskable by I-bit Both X and I bits are both automatically set by Reset or recognition of XIRQ interrupt RTI restores X and I bit to pre-interrupt states

19. Interrupt Vectors Points to the memory address where the Interrupt Subroutine is stored Vector addresses can change depending on whether MON12 is in use or not MON12 calls ISR’s specified by the user in the $0Fxx range The microcontroller calls ISR’s specified in the $FFxx range.

20. Interrupt Vector Table (MON12 in Use) …

21. Interrupt Vector Table (MON12 Not in Use)

22. Resets Forces MCU to: Assume set of initial conditions Begin executing instructions at predetermined starting address Initiated similarly to interrupts by using a vector to define the starting address of code to be run Resets completely stop execution of set of instructions

23. Sources of Resets Power on Reset (POR) Used only for power-up conditions Applying V dd to MCU triggers POR circuit, initiates reset sequence, and starts internal timing circuit 4064 clock cycle delay after oscillator becomes active, allows clock generator to stabilize External Reset (RESET) System reset can also be forced by applying low level to RESET pin External source must hold reset pin low for a total of 6 cycles

24. Sources of Resets Computer Operating Properly (COP) Reset Protects against software failures, such as infinite loops Enabled by setting NOCOP bit in CONFIG register Timer rate controlled in OPTION Register. System E-clock is divided by 2 15 and further scaled by 1, 2, and 4 Clock Monitor Reset Protects against clock failure Set by CME control bit If enabled, the system resets if no MCU clock edges are detected

25. Process Flow out of Resets When Reset is triggered: Program counter loaded with contents of specified address from the vector S, X, and I bits are set in CCR MCU hardware is reset Checks for interrupts that have occurred

26. Standby Modes Suspends CPU operation until reset or interrupt occurs Used to reduce power consumption Two standby modes: WAIT STOP

27. Standby Modes: WAIT Opcode (WAI) Suspends CPU processing CPU registers are stacked On-chip crystal oscillator remains active Peripherals keep running Exit WAIT mode through external IRQ, XIRQ, or any internally generated interrupts

28. Standby Modes: STOP If S-bit in the CCR is 0, CPU goes into Stop mode If S-bit in the CCR is set, opcode is treated as NOP All clocks and internal peripherals are stopped Retains data in Internal RAM if V dd is maintained CPU state and I/O pins are static

29. Standby Modes: STOP Exit STOP mode through external interrupts, pending edge-triggered IRQ, or RESET pin Recovering through XIRQ: X-bit is clear  Returns to stacking sequence leading to normal XIRQ request X-bit is set  Returns to instruction immediately following STOP instruction

30. INTERRUPT PROGRAM EXAMPLE

31. Example Problem: 1ms interrupt Write a routine to interrupt the MC9S12C32 after 1ms of elapsed time. Assume: E = 8 Mhz, Prescaler = 1, MON12 in use Use IOC3 channel to generate interrupt request IOC3 will be used in output compare mode (OC3) Standard timer channel 3 interrupt will be sent

33. Timer Module and Port T IOC3 will be used in output compare mode

34. Write a routine to interrupt the MC9S12C32 after 1msec of elapsed time. TC3HIEQU$0056/* IOC3 output compare register */ TIOSEQU$0040/* Input capture or output compare mode select */ TIEEQU$004C/* Timer interrupt enable register */ TFLG1EQU$004E/* Timer interrupt flag register 2 */ TCTL2EQU$0049/* Timer control register 2 */ TCNTEQU$0044/* Timer count register */ IOC3ISREQU$2000/* Location of IOC3 interrupt service routine */ IOC3VECEQU$0FE8/* Location of IOC3 interrupt vector */ BIT3HIEQU%00001000/* Bit 3 set HIGH, all others LOW */ DLYIOMSEQU8000/* Number of delay cycles. 8000 cycles = 1ms */ ORG$1000 SEI/* Set I bit in CCR to mask interrupts during this routine*/ LDAA #BIT3HI /* BIT3HI = %00001000 */ STAATIOS/* Configure IOC3 as output compare */ STAATIE/* Enable IOC3 interrupt generation */ STAATFLG1/* Clear IOC3 interrupt flag*/ LDAB#%11000000 STAB TCTL2/* Successful compare will set PT3 high */ LDX#IOC3ISR/* IOC3ISR = $2000, starting address of ISR */ STXIOC3VEC/* IOC3VEC = $0FE8, high byte ($20) stored in $0FE8, low byte ($00) stored in $0FE9 */ LDDTCNT/* Read current count from timer count register */ ADDD#DLYIOMS/* Add delay of 8000 cycles (=1ms) */ STDTC3HI CLI/* Clear I bit in CCR to allow maskable interrupts */ 1: Assign values to labels 2: Delay unwanted interrupts 3: Set timer registers 4: Store ISR 5: Set delay & unmask Example Problem: 1ms interrupt

35. Step 1: Assign values to labels TC3HIEQU$0056/* IOC3 output compare register*/ TIOSEQU$0040/* Input capture/output compare select*/ TIEEQU$004C/* Timer interrupt enable register*/ TFLG1EQU$004E/* Timer interrupt flag register 2 */ TCTL2EQU$0049/* Timer control register 2*/ TCNTEQU$0044/* Timer count register*/ IOC3ISREQU$2000/* Location of IOC3 ISR*/ IOC3VECEQU$0FE8/* Location of IOC3 interrupt vector*/ BIT3HIEQU%00001000/* Bit 3 set HIGH, all others LOW*/ DLYIOMSEQU8000/* 8000 cycles = 1ms*/ Treat these as named constants EQU is an assembler directive (not a CPU instruction!) Register addresses found in MC9S12C32 Device User Guide Register details found in TIM_16B8C Block User Guide

36. Step 2: Delay unwanted interrupts ORG$1000 SEI/* Set I bit in CCR to mask interrupts */ /* Clear I bit at the end of our routine */ Alternatively, ORG$1000 LDD#$FFFF/* Set output compare reference to maximum */ STDTC3HI/* Store output compare reference */ Understand why both work. What are the differences? Example Problem: 1ms interrupt

37. Step 3: Write to timer registers LDAA #BIT3HI /* BIT3HI = %00001000 */ STAATIOS/* Configure IOC3 as output compare (IOS3)*/ STAATIE/* Enable IOC3 Interrupt bit (C3I)*/ STAATFLG1/* Clear IOC3 Interrupt Flag bit (C3F) */ LDAB#$C0/* #$C0 = #%11000000 */ STAB TCTL2/* Successful compare will set PT3 high */ Configure desired settings using the timer registers OM3OL3OL0 TCTL2$0049 OM2OL2OM1OL1OM0 01234567 C7FC6FC0F TFLG1$004E C5FC4FC3FC2FC1F 01234567 C7IC6IC0I TIE$004C C5IC4IC3IC2IC1I 01234567 IOS7IOS6IOS0 TIOS$0040 IOS5IOS4IOS3IOS2IOS1 01234567 Example Problem: 1ms interrupt

38. Step 4: Store ISR LDX#IOC3ISR/* IOC3ISR = $2000, starting address of ISR*/ STXIOC3VEC/* IOC3VEC = $0FE8, high byte ($20) stored in $0FE8 and low byte ($00) stored in $0FE9 */ In this example, ISR is located in $2000 Standard timer channel 3 interrupt vector is $0FE8 (hi) : $08FE9 (lo) when MON12 is in use Example Problem: 1ms interrupt

39. Step 5: Set delay and interrupt LDDTCNT/* Read current count from timer count register*/ ADDD#DLYIOMS/* DLYIOMS = 8000. 8000 cycles = 1ms delay*/ STDTC3HI CLI/* Clear I bit */ TCNT is a 16-bit up-counter based on the bus clock Read in count from TCNT and add 8000, store contents in IOC3 output compare register Clear I bit in CCR to enable maskable interrupts Approximately 1ms after this section, a Standard timer channel 3 interrupt request will be sent to the CPU Example Problem: 1ms interrupt

40. PHOTOTRANSISTORS*, OPTO-ISOLATORS*, TRIACS, AND THERMISTORS * = USED IN ME 4447/6405

41. Phototransistors Behave like regular transistors, but: Use light-sensitive collector-base junction to control collector- emitter current (I CE ) Base often unconnected, otherwise biased to adjust sensitivity to light Small collector-emitter leakage current when no light is incident, called dark current

42. Phototransistor Structure and Packaging http://www.radio- electronics.com/info/data/semicond/ phototransistor/photo_transistor.php

43. Phototransistor Application: Obstacle Detection Adjust baffle length to vary detection range Use IR LED and Photodiode to avoid visible light interference Use multiple sensors in a row to detect narrow obstacles

44. Phototransistors: Additional Notes Must be properly biased (as with regular transistors) Used in linear and saturation/cut-off regions Sensitive to temperature changes Must be protected against moisture Hermetic packaging more expensive, but more tolerant of severe environments than plastic packaging

45. Optoisolators Combines IR LED with IR photodiode Operates similar to relays Used to control high voltage devices Excellent noise isolation because switching circuits are electrically isolated Eliminates need for common ground between circuits

46. Optoisolators are like relays Optoisolator Relay

47. Optoisolator Structure Glass dielectric separates input from output Planar Silicon dome

48. Optoisolator Application Transmitting analog or digital signals between circuits, esp. with mismatched voltages, noise issues, inductive loads Arduino isolated from relay drivers: http://arduino- info.wikispaces.com/RelayIsolation  To Arduino

49. Optoisolators: Additional Notes Non-transistor optoisolators exist Resistive optoisolator (photoresistor output) Diode optoisolator (photodiode output) Optoisolated SCR (thyristor output) Optoisolated TRIAC (TRIAC output) Solid-state relay Relevant parameters for comparison: Current Transfer Ratio (output current/input current) Maximum output voltage Input current, required for activating input transmitter Bandwidth Speed

50. Triacs (Triode for Alternating Current) Conducts current in either direction when triggered, until current drops below holding current threshold Bidirectionality makes TRIACs excellent AC switches Can handle large power flows (hundreds of amps / thousands of watts) Effectively based on thyristors

51. Triacs and Thyristors Triacs are effectively 2 thyristors back-to-back Thyristor Triac

52. Triac Structure

53. Triac Applications High Power TRIACS Switching for AC circuits, allowing the control of very large power flows with milliampere-scale control currents Can eliminate mechanical wear in a relay Low Power TRIACS Light bulb dimmers (switching AC wave) Motor speed controls for electric fans and other AC motors Heater control Modern computerized control circuits in household appliances

54. Triac Application: Light dimmer Switching of waveform varies power transmission

55. Triacs: Additional Notes Pros: Better than a transistor in current surge rating – it can handle more current, as it simply turns on more Cheaper than relays Cons: Cannot open switch with gate; must reduce current through the device below its holding current to turn off Relevant parameters: Gate signal requirements Voltage drop Steady-state/holding current Peak current (maximum amount to handle surge)

56. Thermistors Temperature sensitive resistors Change in resistance is very large and precise in relation to change in temperature Exhibit larger resistance change with temperature than thermocouples and RTD’s Thermistor resistance (sensitive in small T range) RTD resistance (stable over large T range) Thermocouple voltage (versatile) T V or R

57. Thermistor Characteristics Extremely non-linear (high process dependency) An individual thermistor curve can be very closely approximated by using the Steinhart-Hart equation: = T = Degrees Kelvin R = Resistance of the thermistor A,B,C = Curve-fitting constants

58. Thermistor Characteristics Wheatstone bridge with selector switch to measure temperature at several locations

59. Thermistors: Additional Notes Generally composed of semiconductor materials Very fragile and prone to permanent decalibration Most have a negative temperature coefficient (NTC); resistance decreases with increasing temperature Positive temperature coefficient (PTC) thermistors also exist with directly proportional R vs. T. Common ranges are -100°F (-75°C) to +300°F (150°C); Some can reach up to 600°F

60. References Interrupt program example: 1ms interrupt Timer module register details from TIM_16B8C Block User Guide Phototransistors http://www.radio-electronics.com/info/data/semicond/phototransistor/photo_transistor.php Optoisolators http://arduino-info.wikispaces.com/RelayIsolation http://yourduino.com/sunshop2/index.php?l=product_detail&p=218 Triacs http://www.radio-electronics.com/info/data/semicond/triac/what-is-a-triac-basics-tutorial.php http://www.digikey.com/us/en/techzone/lighting/resources/articles/Dimming-LEDs-with- Traditional-TRIAC-Dimmers.html http://www.digikey.com/us/en/techzone/lighting/resources/articles/Dimming-LEDs-with- Traditional-TRIAC-Dimmers.html http://www.circuitstoday.com/diac-applications Thermistors http://www.radio-electronics.com/info/data/resistor/thermistor/thermistor.php Previous student lectures Interrupts, Thermistors, Opto-isolators and Phototransistors – Fall 2009 – Kipp Schoenwald, Stephen Hunte, Joseph Storey DACs and Triacs – Fall 2009 – Wye-Chi Chok

61. Questions?