1. Switching rules Either A+ or A– is always closed, but never at the same time * Either B+ or B– is always closed, but never at the same time * *same time closing would cause a short circuit from Vdc to ground Corresponding values of Va and Vb A+ closed, Va = Vdc A– closed, Va = 0 B+ closed, Vb = Vdc B– closed, Vb = 0 H BRIDGE Vdc Load A+B+ A–B– VaVb

2. Corresponding values of Vab A+ closed and B– closed, Vab = Vdc A+ closed and B+ closed, Vab = 0 B+ closed and A– closed, Vab = –Vdc B– closed and A– closed, Vab = 0 The free wheeling diodes permit current to flow even if all switches did open These diodes also permit lagging currents to flow in inductive loads H BRIDGE Vdc Load A+B+ A–B– VaVb

3. Figure 1. V cont, –V cont, and V tri V cont –V cont V tri But is a square wave output good enough? Not for us! Sinusoidal load voltage is usually the most desirable. But how do we approximate a sinusoidal output with only three states (+Vdc, –Vdc, 0) ? The answer: Unipolar PWM modulation Vcont > Vtri, close switch A+, open switch A–, so voltage Va = Vdc Vcont < Vtri, open switch A+, close switch A–, so voltage Va = 0 –Vcont > Vtri, close switch B+, open switch B–, so voltage Vb = Vdc –Vcont < Vtri, open switch B+, close switch B–, so voltage Vb = 0

4. A + closed, A – open, so V a in Figure 2 = V dc. Else A – closed, A + open, so V a = 0. B + closed, B – open, so V b in Figure 2 = V dc. Else B – closed, B + open, so V b = 0.

5. V dc Idealized Load Voltage (V a – V b ) Waveform –V dc 0

6. ma = 0.50 (linear region)

7. ma = 1.5 (overmodulation region)

8. Figure 6. Variation of RMS value of no-load fundamental inverter output voltage (V 1rms ) with m a mama 0 1 V 1rms linear overmodulation saturation asymptotic to square wave value

9. 2mf cluster 4mf cluster Table 1. Load voltage harmonic RMS magnitudes with respect to (for large mf ) Harmonic ma = 0.2 ma = 0.4 ma = 0.6 ma = 0.8 ma = 1.0 1 (fundamental)0.2000.4000.6000.8001.000 2mf ± 10.1900.3260.3700.3140.181 2mf ± 30.0240.0710.1390.212 2mf ± 50.0130.033 4mf ± 10.1630.1570.0080.1050.068 4mf ± 30.0120.0700.1320.1150.009 4mf ± 50.0340.0840.119 4mf ± 70.0170.050

11. 4” Jack for AC wall wart Jack for DC wall wart –12Vdc isolated rail +12Vdc isolated rail 2W, DC-DC converter 500Ω pot for adjusting V cont Protoboard common (i.e., the green wires) Figure 8a. The 10” long piece of 1” x 6” wood piece with inverter control circuit mounted in the lower 4” You will build this part the following week

12. Figure 8b. Zoom-in of protoboard Mount triangle wave generator IC upside down to minimize wiring clutter 2W, DC-DC converter +12Vdc isolated rail (red) –12Vdc isolated rail (violet) Protoboard common (i.e., the green wires) Input from 12Vdc regulated wall wart Isolated outputs from 2W, DC-DC converter (red = +12V, violet = –12V, green = common) Zoom-in of DC-DC converter

14. Triangle wave generator

15. Dual Op Amp

16. Dual Comparator

17. Figure 10. Rise and fall times of the triangle wave Approx. equal rise and fall times

18. Figure 12. Output control voltages V(A +,A – ) and V(B +,B – ), with respect to protoboard common, with V cont = 0 (i.e., the m a = 0 case)

19. Figure 15. Idealized V load, with m a just into the overmodulation region Figure 16. Idealized V load observed in the scope averaging mode, with m a in the linear region

20. Figure 17. Idealized V load observed in the scope averaging mode, with m a just into the overmodulation region Figure 18. Idealized V load observed in the scope averaging mode, with m a almost into the saturation (i.e., square wave) region

21. Figure 19. FFT of idealized V load in the linear region with m a ≈ 1.0, where the frequency span and center frequency are set to 100kHz and 50kHz, respectively 2m f cluster (46kHz) 4m f cluster (92kHz) 60Hz component

22. Figure 23. Near saturation, the 3 rd harmonic magnitude is 0.30 of the fundamental Figure 24. Near saturation, the 5 th harmonic magnitude is 0.13 of the fundamental

23. One firing circuit for each MOSFET, with each firing circuit mounted on a separate protoboard. A – and B – can share a power supply and ground. A + and B + must each use separate power supplies and grounds. Do not connect any of these grounds to the ground of the control circuit. O + O – (see Figure 2 for connections) Powered by +12Vdc regulated supply (isolated from control circuit) 10kΩ 0.1µF 10Ω 1.2kΩ MOSFET G D S 100kΩ 5 4 Opto 8 1 5 4 Driver 8 1 Figure 1. Isolated firing circuit with optocoupler and gate driver Outline of protoboard A + and B + use inverting drivers. A – and B – use non-inverting drivers. The optocouplers provide an additional inversion. green blue for A +,B +, violet for A –,B – blue red blue Grounds (isolated from control circuit) Wait until next week

24. Figure 2. Physical layout of firing circuits (A + opto and driver are powered by a 12Vdc isolated DC-DC converter. Likewise, B+ has a 12Vdc isolated DC-DC converter. A – and B – are powered by the DC wall wart.) Individual protoboard for each firing circuit Optically-isolated firing circuits. Mount drivers near the MOSFETs A + Firing A – Firing B + Firing B – Firing Control Circuit from Previous Lab Jack for DC wall wart O + O – V(A +,A – ) V(B +,B – ) –12Vdc regulated blue violet Jack for AC wall wart 8”

25. Figure 3. Layout of inverter control circuit and isolated firing circuits

26. Figure 4. Zoom-in view of A + and A – isolated firing circuits DC-DC converter for A +

27. Pin configuration for 6N136 optocoupler

28. Input from 12Vdc wall wart Isolated output

29. V(A+,A–) – V(B+,B–) with control circuit driving optos

30. V(A +,A – ) Opto A + output V(A +,A – ) Opto A – output We want the opto output waveforms to look identical in this test in order to preserve symmetry in firing

31. Opto A + output Opto A – output

32. V(A +,A – ) A + driver output V(A +,A – ) A – driver output

33. A + driver output A – driver output We want no overlap in driver “on” times, so there will be no idling current After finishing A + and A -, perform same checkout for B + and B -

34. Figure 1. Physical layout of inverter MOSFET A + MOSFET A – MOSFET B + MOSFET B – H-Bridge and Filters Individual heat sink for each MOSFET – Vdc + – Vac (Output) + b a A + Firing A – Firing B + Firing B – Firing Control Circuit from Previous Lab Jack for DC wall wart O + O – V(A +,A – ) V(B +,B – ) –12Vdc regulated blue violet Jack for AC wall wart

36. Vdc Input Power 10µF, 50V, high- frequency capacitor – Vdc + Figure 2. Zoom-in of filter details for Vdc input and Vac output sections of Figure 1 (points “a” and “b” correspond to the two sides of the inverter output) 10µF, 50V, bipolar, high-frequency capacitor 100µH, 9A or 10A inductor – Vac + Point “a” in H-bridge Point “b” in H-bridge

37. Figure 3. H-Bridge wiring color scheme (using #16 stranded) (note – wire crossings are not connected) A + A – B + B – G D S – Vdc + – Vac + red orange blue black

39. V GS of A + V GS of A – blanking time to eliminate overlap actual MOSFET turn on

40. + V DS of A + – V DS of A – + A + off A – on A + on A – off + V DS of B + – V DS of B – + B + off B – on B + on B – off Note - the added vertical bars show slight overlap in “on” times, but only during the transitions.

41. Vac, without and with filter

42. Vac with Vcont near saturation