1. finger Sci (SA) Beam profile wire chamber 727 TEST BEAM SETUP Jul-Aug2012 (27.07.2012-10.08.2012) Si3 Si6 Y-inverted 26 Jura 1155 50 TOP VIEW SIDE VIEW Si1 26 s1 s640 New movable table (π -, -80 GeV/c) z x z y y x x veto Sci SB SD 5 SB Saleve 170 15 SC 5 Si1 26 s1 s640 Si6 Y-inverted 26 Si3 26 s1 s640 42 16 Info: T1-8, p=0.4mm, sw=0.3mm, gp=5mm X X X X X X X X T1 T2 T3 T4 T5 T6 T7 T8 XY Tmm3 Tmm2 XY Tmm5 X X X X X X X X T1 T2 T3 T4 T5 T6 T7 T8 XY Tmm3 Tmm2 XY 120 Freiburg frame -θ-θ Info: Tmm2-6, p=0.250mm, sw=0.150mm, gp=5mm XY Tmm6 XY 1250 205 (π -, -120GeV/c after Mon 30.07) Tmm6 Tmm5 s1 s64 s256 s1 s256 1480

5. x x x Ineffic= π(d 2 /4)/L 2 =0.011 for d=0.3mm & L=2.5mm L d pillars Efficiency

6. x x x missing Missing cluster positions pilar

7. Angle Resolution Normal tracks x x x x Theta (rad) 0.22mrad 0.23mrad

8. x x x T1 T3 T5 T7 Position Resolution

9. x x x T2 T4 T6 T8

10. Theta=20 degrees uTPC mode

11. T12 T34 T56 T78 ?

12. Theta=30 degrees

13. T12 T34 T56 T78 ?

14. Theta=40 degrees

15. T12 T34 T45 T56 ?

16. Earliest time of T1 & T2 Earliest time

17. mm VMM1 card Flat cable AZ adapter BNL DAQ card Analog Amplitude & time Lemo cables Avnet LX9 switch x16 mmdaq PC SDC RJ45 USB Power supply 8A/5V CL & trigger Sci trigger APV SRS FEC Mezz card FPGA Virtex-7 Trigger Eval board CL & trigger distribution RJ45 Fast trigger out (LVDS) x16 Monitor out VMM1 Readout System July 2012 x16

18. To Ethernet switch mMegas Detector FPGA Trigger Processor Address in Real Time 8 planes VMM1 Control And Digitizer Trigger & Clock From SRS (Givi’s card) Trigger/Clock Distribution Monitor Analog Amplitude And Time

19. Theta=30 degrees

21. T12 T34 T56

22. 30 o 20 o 10 o 540V 530V 520V 30 o 20 o 10 o 540V 530V 520V