1. III. Multicore Processors (3)
Dezső Sima
Spring 2007
(Ver. 2.0)
 Dezső Sima, 2007

2. 10.1.3 Dual/quad-core server processors
Dual-Core Xeon UP-lines
Dual/Quad-Core Xeon DP-lines
Dual-Core Xeon MP-lines

3. 10.1.3 Dual/quad-core server processors
Dual-Core Xeon UP-lines
Xeon line
Core 2 Duo
9/2006
60 nm
(Core based, monolithic, dual-core)

4. Table: Main features of the dual-core Xeon 3000 UP-line
Xeon 3000 UP-line (Conroe)
Xeon 3000 line (1)
Series
3000 (Conroe)
Dual/Quad-Core DC
Models
Microarchitecture
Core
Cores
E6300-E6700
Intro.
9/2006
Technology
65 nm
Die size
143 mm2
Nr. of transistors
291 mtrs
fc [GHz] L2
2*4 MB
FSB [MT/s]
1066
TDP [W] 65
Socket
FC-LGA6
EM64T HT ED VT
EIST
La Grande
AMT2
Table: Main features of the dual-core Xeon 3000 UP-line
Surces: Intel, Wikipedia

5. 10.1.3 Dual/quad-core server processors
Dual/Quad-Core Xeon DP-lines
Xeon DP 2.8
Paxville DP
10/2005
90 nm
(Netburst based, multi-chip, two Irwindale cores)
Xeon 5000 line
Dempsey
5/2006
65 nm
(Netburst based, multi-chip, two Cedar Mill cores)
Xeon 5100 line
Woodcrest
6/2006
65 nm
(Core based, monolithic, dual-core)
Xeon 5300 line
Clovertown
11/2006
65 nm
(Core based, multi-chip, two Woodcrest chips)

6. 10.1.3 Xeon DP 2.8 (Paxville DP) (1)
Intel’s first 64-bit Xeon
Nocona
Irwindale
Nocona
Paxville
(L2 enlarged to 2MB)
(2 x Irwindale cores)
(DP enhanced Prescott)
(DP enhanced Prescott 2M)
6/2004
10/2004
90 nm
112 mm2
125 mtrs
Xeon DP 2.8 – 3.4
Xeon DP 2.8J - 3.4J
mPGA 604
2/2005
9/2005
90 nm
135 mm2
169 mtrs
Xeon DP 2.8 – 3.6
Xeon DP 3.8
mPGA 604
10/2005
11/2005
90 nm
2 x 135 mm2
2 x 169 mtrs
Xeon DP 2.8
Xeon MP
mPGA 604
In contrast: corresponding
desktop processors have
the LGA 775 socket.
Figure: Genealogy of the Xeon Paxville core
Sources:

7. 10.1.3 Xeon DP 2.8 (Paxville DP) (2)
Heat Sink
Die
Die size capacitors
FC-mPGA4 package
Package pin
Pin side capacitors
The FC-mPGA package interfaces with the motherboard via an mPGA604 socket
Figure: Packaging of the Paxville processor
Source: - „Dual-Core Intel Xeon Processor 2.80 GHz Datasheet,” Oct. 2005,

8. 10.1.3 Xeon DP 2.8 (Paxville DP) (3)
Figure Connecting the two Irwindale cores in the large Paxville Package (?)
Source: Douglas J., „Intel 8xx series and Paxville Xeon-MP Microprocessors,”

9. 10.1.3 Xeon DP 2.8 (Paxville DP) (4)
Figure: Packaging of the Paxville
(two Irwindale dies are mounted on a carrier and the carrier is packaged as a 604 package”
Source: Conolly C., „Intel Paxville Dual Core Xeon and the ASsus PVL-D Intel 7520,” Oct. 2005,

10. 10.1.3 Xeon DP 2.8 (Paxville DP) (5)
PGA 604
135
800
2*2 MB
2.8
2*169 mtrs
2*135 mm2
90 nm
10/2005
2*Irwindale dies
Netburst
Xeon DP 2.8 DC
(Paxville DP)
AMT2
La Grande
EIST VT ED HT
EM64T
Socket
TDP [W]
FSB [MT/s] L2
fc [GHz]
Nr. of transistors
Die size
Technology
Intro.
Cores
Microarchitecture
Models
Dual/Quad-Core
Series
Table: Dual-Core Xeon DP-lines (1)
Sources: Intel, Wikipedia

11. 10.1.3 Xeon 5000 DP-line (Dempsey) (1)
Figure: Block diagram of the Dempsey (Cedar Mill-based)
Source: Inkley B. and Tetrick S., „Intel Multi-core Architecture and implementations,” IDF, March 2006,

12. 10.1.3 Xeon 5000 DP-line (Dempsey) (2)
Figure: Packaging of the Dempsey

13. 10.1.3 Xeon 5000 DP-line (Dempsey) (3)
Figure: The Xeon DP Dempsy with the two FSB capable Blackford chipset
Source: Brookwood N., The Role of intellignet Desing i the Evolution of Multi-Core Processors,” Febr

14. 10.1.3 Xeon 5000 DP-line (Dempsey) (4)
LGA 771
95/130
667/1066
2*2 MB
2*188 mtrs
2*81 mm2
65 nm
5/2006
2*Cedar Mill dies
Netburst DC
5000 (Dempsey)
PGA 604
135
800
2.8
2*169 mtrs
2*135 mm2
90 nm
10/2005
2*Irwindale dies
Xeon DP 2.8
(Paxville DP)
AMT2
La Grande
EIST VT ED HT
EM64T
Socket
TDP [W]
FSB [MT/s] L2
fc [GHz]
Nr. of transistors
Die size
Technology
Intro.
Cores
Microarchitekture
Models
Dual/Quad-Core
Series
Table: Dual-Core Xeon DP-lines (2)
Sources: Intel, Wikipedia

15. 10.1.2 Xeon 5100 DP-line (Woodcrest) (1)
Figure: Block diagram of the Merom, Conroe and Woodcrest processors
Source: Inkley B. and Tetrick S., „Intel Multi-core Architecture and implementations,” IDF, March 2006,

16. 10.1.3 Xeon 5100 DP-line (Woodcrest) (2)
Figure: Die shot of the Woodcrest (5100 series) processor (L2: 4 MB)
Source:

17. 10.1.3 Xeon 5100 DP-line (Woodcrest) (3)
Merom
Conroe
Woodcrest
Figure: Contrasting the die shots of Merom, Conroe and Woodcrest
Sources: Kubicki K., „Intel 2006 Mobile CPU Roadmap Update,” Mai 2006,
Hübner, T., „Intel Core 2 Duo E6700 und E6600,” July 2006,

18. 10.1.3 Xeon 5100 DP-line (Woodcrest) (4)
LGA 771
95/130
667/1066
2*2 MB
2*188 mtrs
2*81 mm2
65 nm
5/2006
2*Cedar dies
Netburst DC
5000 (Dempsey)
PGA 604
135
800
2.8
2*169 mtrs
2*135 mm2
90 nm
10/2005
2*Irwindale dies
Xeon DP 2.8
(Paxville DP)
AMT2
La Grande
(5140 or above)
EIST VT ED HT
EM64T
Socket
65/80
TDP [W]
1066/1333
FSB [MT/s]
4 MB L2
fc [GHz]
291 mtrs
Nr. of transistors
143 mm2
Die size
Technology
6/2006
Intro.
Single dies
Cores
Core
Microarchitekture
Models
Dual/Quad-Core
5100 (Woodcrest)
Series
Table: Dual-Core Xeon DP-lines (3)
sources: Intel, Wikipedia

19. 10.1.3 Xeon 5300 DP-line (Clovertown) (1)
Figure: The Xeon 5300 series (Clovertown) dies are built up of two dual core Woodcrest
Source: Li W. and Babayan B., „Extracting The Most Out Of Intel’s Multi-Core Platforms with Software,”

20. 10.1.3 Xeon 5300 DP-line (Clovertown) (2)
Figure: Packaging the Clowertown
Source: Wasson S., „Intel’s Woodcrest procdessor previewed,” May 2006,

21. 10.1.3 Xeon 5300 DP-line (Clovertown) (3)
LGA 771
95/130
667/1066
2*2 MB
2*188 mtrs
2*81 mm2
65 nm
5/2006
2*Cedar dies
Netburst DC
5000 (Dempsey)
PGA 604
135
800
2.8
2*169 mtrs
2*135 mm2
90 nm
10/2005
2*Irwindale dies
Xeon DP 2.8
(Paxville DP)
AMT2
La Grande
(5140 or above)
EIST VT ED HT
EM64T
Socket
80/120
65/80
TDP [W]
1066/1333
FSB [MT/s]
2*4 MB
4 MB L2
fc [GHz]
2*291 mtrs
291 mtrs
Nr. of transistors
2*143 mm2
143 mm2
Die size
Technology
11/2006
6/2006
Intro.
2*Woodcrest dies
Single dies
Cores
Core
Microarchitekture
E /X5355
Models QC
Dual/Quad-Core
5300 (Clovertown)
5100 (Woodcrest)
Series
Table: Dual-Core Xeon DP-lines (4)
Sources: Intel, Wikipedia

22. 10.1.3 Dual/quad-core server processors
Dual-Core Xeon MP-lines
Xeon 7000 line
Paxville MP
11/2005
90 nm
(Netburst based, multi-chip, two Irwindale dies)
Xeon 7100 line
Tulsa
8/2006
65 nm
(Netburst based, monolithic, Cedar Mill based)

23. 10.1.3 Xeon 7000 MP-line (Paxville MP) (1)
Xeon 7000 line (Paxville MP) (1)
Xeon 7000 MP-line (Paxville MP) (1)
AMT2
La Grande
EIST VT ED HT
EM64T
PGA604
Socket
95/150
TDP [W]
667/800
FSB [MT/s] L3
2*1/2 MB 1 L2
fc [GHz]
2*169 mtrs
Nr. of transistors
2*135 mm2
Die size
90 nm
Technology
11/2005
Intro.
2*Irwindale dies
Cores
Netburst
Microarchitecture
Models DC
Dual/Quad-Core
7000 (Paxville MP)
Series
1 Concerning the L2 cache size, there is a contradiction in Intel’s documentation; whereas according to the data sheets models of the 7000 series include 1 or 2 MB L2 caches the comparison charts for all models 1 MB large L2 caches.
Table: Dual-Core Xeon MP-lines (1)
Sources: Intel, Wikipedia

24. 10.1.3 Xeon 7100 MP-line (Tulsa) (1)
Figure: Block diagram and die shot of Tulsa
Source: Rusu S., „Circuit Technologies for Multi-Core Processor Design,” April 2006,

25. 10.1.3 Xeon 7100 MP-line (Tulsa) (2)
Figure: Detailed block diagram of Tulsa (Cedar Mill-based)
Source: Inkley B. and Tetrick S., „Intel Multi-core Architecture and implementations,” IDF, March 2006,

26. 10.1.3 Xeon 7100 MP-line (Tulsa) (3)
Figure: Die shot of Tulsa (L3: 16 M)
Source: Vance A., „Intel completes Operation Catch up with Tulsa release,” The Register, Aug. 2006,

27. 10.1.3 Xeon 7100 MP-line (Tulsa) (4)
(435 mm2)
Cedar Mill
(81 mm2)
2 x 2 MB L2
2 x 1 MB L” + 16 MB L3
Figure: Contrasting the Cedar Mill and Tulsa die shots
Sources: Huynh T., „Pressler: Intel Extreme Edition 955,” Dec. 2005,
Vance A., „Intel completes Operation Catch up with Tulsa release,” The Register, Aug. 2006,

28. 10.1.3 Xeon 7100 MP-line (Tulsa) (5)
AMT2
La Grande
EIST VT ED HT
EM64T
PGA604
Socket
95/150
TDP [W]
667/800
FSB [MT/s]
4/8/16 MB L3
2*1 MB
2*1/2 MB 1 L2
fc [GHz]
1328 mtrs
2*169 mtrs
Nr. of transistors
435 mm2
2*135 mm2
Die size
65 nm
90 nm
Technology
8/2006
11/2005
Intro.
Cedar Mill-based single die
2*Irwindale dies
Cores
Netburst
Microarchitekture
7110M-7140M / 7110N-7150N
Models DC
Dual/Quad-Core
7100 (Tulsa)
7000 (Paxville MP)
Series
1 Concerning the L2 cache size, there is a contradiction in Intel’s dokumentation; whereas according to the data sheets models of the 7000 series include 1 or 2 MB L2 caches the comparison charts for all models 1 MB large L2 caches.
Table: Dual-Core Xeon MP-lines (2)
Sources: Intel, Wikipedia

29. 10.1.3 Guessed road map of Intel processors (1)
Category
Code Name
Cores
Cache
Market
Desktop
Kentsfield
Dual core multi-die
4 MB
Mid 2007
Conroe
Dual core single die
4 MB shared
End 2006
Allendale
2 MB shared
Cedar Mill (NetBurst/P4)
Single core
512 kB, 1 MB, 2 MB
Early 2006
Presler (NetBurst/P4)
Dual core, dual die
Desktop/Mobile
Millville
1 MB
Early 2007
Mobile
Yonah2
Dual core, single die
2 MB
Yonah1
1/2 MB
Mid 2006
Stealey
512 kB
Merom
2/4 MB shared
Enterprise
Sossaman
Woodcrest
Clovertown
Quad core, multi-die
Dempsey (NetBurst/Xeon)
Tulsa
4/8/16 MB
Whitefield
Quad core single die
8 MB, 16 MB shared
Early 2008
Figure 5.7: Future 65 nm processors (Overview)
Source: P. Schmid: Top Secret Intel Processor Plans Uncovered

30. 10.1.3 Guessed road map of Intel processors (1)
Codename
Cores
Cache
Market
Desktop
Wolfdale
Dual core, single die
3 MB shared
2008
Ridgefield
Dual core single die
6 MB shared
Yorkfield
8 cores multi-die
12 MB shared
2008+
Bloomfield
Quad core, single die -
Desktop/Mobile
Perryville
Single core
2 MB
Mobile
Penryn
3 MB, 6 MB shared
Silverthorne
Enterprise
Hapertown
Figure 5.8: Future 45 nm processors (overview)
Source: P. Schmid: Top Secret Intel Processor Plans Uncovered

31. 10.1 Published road map of Intel processors
Figure: Roadmap of Intel’s lines
Source: Thrax, „ Core 2 Duo and the future of Intel,” Nov. 2006,

32. 10.1.4 Dual/quad-core Itanium processors
Dual/quad-core Itanium 2 lines
Dual-core Itanium 2
Montecito
7/2006
90 nm
(Itanium 2 based, monolithic)
Quad-core Itanium 2
Tukwila
2008
65 nm
(Itanium 2 based, monolithic)

33. 10.1.4 Dual-core Itanium 2 (Montecito) (1)
Figure: Block diagram and basic floor plan of the Montecito
Source: Rusu S., „Circuit Technologies for Multi-Core Processor Design,” April 2005,

34. 10.1.4 Dual-core Itanium 2 (Montecito) (2)
Figure: Block diagram of the Itanium 2 processor
Source: McNairy C. and Soltis D. „ Itanium 2 Processor Microarchitecture,” IEEE Micro, March-April 2003, pp

35. 10.1.4 Dual-core Itanium 2 (Montecito) (3)
Figure: Block diagram of the Montecito
McNairy C. and Bhatia R., „Montecito,” IEEE Micro, March-April 2005, pp

36. 10.1.4 Dual-core Itanium 2 (Montecito) (4)
Figure: New features of Montecito
Source: Intel

37. 10.1.4 Dual-core Itanium 2 (Montecito) (5)
Figure: Floor plan of Montecito
Source: Naffziger S. et al., „The Implementation of a 2-core Multi-Threaded Itanium-Family Processor,”
Proc. ISSCC, 2005, pp , 592

38. 10.1.4 Dual-core Itanium 2 (Montecito) (6)
Madison (130 nm)
Montecito (90 nm)
(Inthe figure reduced to 90 nm)
L2: 256 KB, L3: 9 MB
L2I: 1 MB, L2D: 256 KB, L3: 12 MB
Figure: Contrasting Itanium 2 Madison and Montecito (at the same feature size)
Source: Krewell K., „Best Servers of 2004,” Microprocessor Report, Jan. 2005,
Naffziger S. et al., „The Implementation of a 2-cre Multi-Threaded Itanium-Family Processor,”
Proc. ISSCC, 2005, pp , 592

39. 10.1.4 Dual-core Itanium 2 (Montecito) (7)
Figure: Contrasting die sizes and floor plans of Itanium processors
Source: DeMone P., Sizing Up the Super hevyweights,” Real World Technologies, Sept. 2004,

40. 10.1.4 Dual-core Itanium 2 (Montecito) (8)
104
533
2*4 MB
1.6
9030
1 MB I$ KB D$ per core L2
Dual-Core Itanium 2 (Montecito)
Series 75
2*3 MB
9010
400
2*6 MB
1.40
9015
DBS
(Silvervale)
PAC 611
1.42
1720 mtrs
596 mm2
90 nm
7/2006
9020
2*9 MB
9040
EIST
Cache safe VT ED HT
64-bit
Socket
TDP [W]
FSB (16 B wide) [MT/s]
f HT
2*12 MB L3
fc [GHz]
Nr. of transistors
Die size
Technology
Introduced
Stepping
9050
Models
Table: Main features of the dual-core Itanium 2 line
Sources: Intel, Wikipedia

41. 10.1.5 Quad-core Itanium 2 (Tukwila) (1)
Figure: Expected features of the quad-core Tukwila
Source: Intel

42. 10.1.5 Quad-core Itanium 2 (Tukwila) (2)
Figure: Preliminary die shot of Tukwila
Source: Hoyler G., „Intel Itanium Architecture Roadmap and Technology Update,” 2004,

43. x86 multicore processors
10.1 Literature (1)
x86 multicore processors
Bhandarkar D. „Energy Efficient Performance: The Next Frontier,” Oct. 2006,
Brookwood N., The Role of intellignet Desing in the Evolution of Multi-Core Processors,” Febr
Douglas J., „Intel 8xx series and Paxville Xeon-MP Microprocessors,”
Li W. and Babayan B., „Extracting The Most Out Of Intel’s Multi-Core Platforms with Software,”
Rusu S., „Circuit Technologies for Multi-Core Processor Design,” April 2006,
Shimpi A. L. and Wilson D., Intel Pentium 4 6xx and 3.73EE,” Febr. 2005,
Smith, S.L. and Valentine, B.:”Intel Core Microarchitecture,” March 2006,
NGMA%20IDF%20Press%20Mar%208%20PDF%20Set.pdf
- Related Intel Datasheets,
- Wikipedia

44. 10.1 Literature (2) Montecito
DeMone P., Sizing Up the Super hevyweights,” Real World Technologies, Sept. 2004,
Hoyler G., „Intel Itanium Architecture Roadmap and Technology Update,” 2004,
McNairy C. and Soltis D. „ Itanium 2 Processor Microarchitecture,” IEEE Micro, March-April 2003, pp
McNairy C. and Bhatia R., „Montecito: A Dual-Core, Dual-Thread Itanium Processor,”
IEEE Micro, March-April 2005, pp
Naffziger S. et al., „The Implementation of a 2-core Multi-Threaded Itanium-Family Processor,”
Proc. ISSCC, 2005, pp ,
Naffziger S. et al., The Implementation of a 2-Core, Multi-threaded Itanium Family Processor,
IEEE Journal Solid-State Circuits, Vol. 41, No. 1, Jan. 2006, pp
Rusu S., „Circuit Technologies for Multi-Core Processor Design,” April 2006,
- „Inside the Intel Itanium 2 Processor,” Technical White Paper, July 2002, HP Corp.
- Related Intel Datasheets,