1. 1 Phase-Locked Loop

2. 2 Phase-Locked Loop in RF Receiver BPF1BPF2LNA LO MixerBPF3IF Amp Demodulator Antenna RF front end PD Loop Filter 1/N Ref. VCO Phase- Locked Loop

3. 3 Functional Blocks in PLL Phase detector (PD): find difference between phases of two signals Loop filter: provide appropriate control voltage for the voltage-controlled oscillator (VCO) VCO: generate signals with phase determined by the control voltage Divide-by-N: LO phase changes N times faster than Ref phase PD Loop Filter 1/N Ref VCO Phase- Locked Loop LO

4. 4 Design Issues Tracking behavior Noise performance Jitter characteristics –Jitter tolerance –Jitter transfer –Jitter generation Power consumption

5. 5 System Modeling v Ref : input reference signal v LO : local oscillator (LO) output signal v d : detector output F(s): transfer function of loop filter v C : control voltage for VCO PDF(s) VCO vdvd vCvC v Ref v LO

6. 6 System Modeling Phase signals contain information  Ref : phase of reference signal  LO : phase of local oscillator (LO) signal  e : phase difference between  Ref and  LO PDF(s)  Ref VCO  LO KdeKde v Ref v LO

7. 7 Jump in Phase

8. 8 Ramp in Phase

9. 9

10. 10 Phase Detector V d =K d  e =K d (  REF –  LO ) K d : gain of phase detector KdKd  REF+   LO ee vdvd

11. 11 Loop Filter V C (s) = F(s) V d (s) Low-pass filter –Extract phase error –Remove high frequency noises Passive filter for integrated PLL Active filter for discrete component PLL F(s) vdvd vCvC

12. 12 Passive Lag Filter Lag filter: pole magnitude smaller than zero Passive components: high linearity, gain < 1 vdvd vCvC R1R1 R2R2 C + – + –

13. 13 Active Lag Filter Can adjust pole and zero locations Can have gain Op amp limitations vdvd vCvC R1R1 R2R2 C2C2 + – + – + – C1C1

14. 14 Active Proportional-Integral (PI) Filter Large open loop gain at low frequency Op amp limitations –Linearity –Noise –Open loop gain vdvd vCvC R1R1 R2R2 C + – + – + –

15. 15 Voltage-Controlled Oscillator K VCO : gain of VCO 1/s + 00 K VCO vCvC  LO

16. 16 Transfer Function of PLL Open-loop transfer function from  e to  LO KdKd  REF+   LO ee vdvd 1/s + 0+0+ K VCO vCvC  LO F(s)

17. 17 Transfer Function of PLL Closed-loop transfer function from  REF to  LO KdKd  REF+   LO ee vdvd 1/s + 0+0+ K VCO vCvC  LO F(s)

18. 18 Transfer Function from  REF to  e Closed-loop transfer function KdKd  REF+   LO ee vdvd 1/s + 0+0+ K VCO vCvC  LO F(s)

19. 19 Other TF of Interest Noise in control voltage KdKd  REF+   LO ee vdvd 1/s + v Cn + K VCO vCvC  LO F(s)

20. 20 Other TF of Interest Phase noise of VCO KdKd  REF+   LO ee vdvd 1/s + n+n+ K VCO vCvC  LO F(s)

21. 21 Transfer Functions for Different Loop Filters Passive lag filter Active lag filter Active PI filter

22. 22 Normalizing Transfer Function Normalized denominator Passive lag filter Active lag filter Active PI Filter

23. 23 Normalized Transfer Function Passive lag filter Active lag filter Active PI Filter

24. 24 Normalized Transfer Function Passive lag filter Active lag filter

25. 25 Frequency Response of H(s)

26. 26 Frequency Response of H e (s)

27. 27 Step Response of PLL Phase step Phase Error Steady state error (final value theorem)

28. 28 Step Response

29. 29 Ramp Response of PLL Phase ramp Phase Error Steady state error (final value theorem)

30. 30 Ramp Response

31. 31 General Steady State Error in Ramp Response High loop gain Low loop gain

32. 32 Stability of PLL Criterion for stability –Closed-loop pole at left half plane –Sufficient phase margin Control of pole location –Open loop gain –Open loop zero Check root locus

33. 33 Root Locus Method Closed-loop TF Closed-loop poles make –K=0, open-loop poles –K infinity, open-loop zeros or infinity

34. 34 Root Locus for Passive Lag Filter

35. 35 Root Locus for Active Lag Filter

36. 36 Root Locus for Active PI Filter

37. 37 Root Locus for 1 st -Order LP Filter

38. 38 Effects of Parasitics

39. 39 Effects of Zero

40. 40 Phase Noise and Jitter Phase noise –Fluctuation in phase –Frequency domain –Discussed in RF circuits Jitter –Error in clock edge (period) –Time domain –Significant in communications circuits Two concepts –Related to each other –Exact relationship not clear

41. 41 Jitter Measurements Agilent, “ Understanding Jitter and Wander Measurements and Standards. ”

42. 42 Jitter Tolerance Ability of a PLL to operate with jitter –Applied to its reference –Various magnitudes –Different frequencies Usually specified using an input jitter mask –Jitter magnitude and corner frequencies –BER requirement –Various for standards

43. 43 PLL in Clock and Data Recovery 0 1 0 0 1 0 1 0 1 0 1 0 0 X 1 0 1 0 01 0 0 1 0 1 0 Ideal signal Distorted signal Ideal clock Recovered clock

44. 44 Jitter Tolerance Mask

45. 45 Jitter Tolerance Measurement

46. 46 Jitter Tolerance Measurement

47. 47 Jitter Tolerance Measurement Error at corner frequency –Insufficient clock recovery bandwidth –Incorrect mask used

48. 48 Jitter Tolerance Measurement Excessive jitter tolerance margin Tolerance margin

49. 49 Jitter Tolerance Measurement Occasional fail at specific frequencies –Need extra settling time after jitter amplitude change Repeating with additional settling time Spot measurement

50. 50 Jitter Tolerance Measurement Limited clock recovery bandwidth Eye-width alignment noise

51. 51 Jitter Tolerance Measurement Limited buffer store

52. 52 Jitter Transfer Jitter transfer or jitter attenuation Output jitter vs. input jitter –Input jitter with various amplitudes and frequencies –Output jitter measured with various bandwidths Intrinsic jitter Typically specified using a bandwidth plot –Amplitude –Roll off speed –Corner Frequency

53. 53 Jitter Transfer Mask

54. 54 Jitter Transfer Measurement Jitter tolerance mask used to set input jitter level Sinusoidal jitter at magnitudes and frequencies Narrow-band measurement

55. 55 Jitter Transfer Measurement Different test masks SONET mask: additional amplitude at lower band

56. 56 Jitter Transfer Measurement Measurement set-up noise -40 dB sufficient

57. 57 Jitter Transfer Measurement Low-frequency phase noise Power-line crosstalk Short measurement time

58. 58 Jitter Transfer Measurement Incorrect filter characteristic Excessive peaking

59. 59 Jitter Transfer Plot E. Barari, “ Jitter Analysis / Specification, ” May 2002.

60. 60 Measured Jitter Transfer Characteristic E. Barari, “ Jitter Analysis / Specification, ” May 2002.

61. 61 Measured Jitter Transfer Characteristic E. Barari, “ Jitter Analysis / Specification, ” May 2002.

62. 62 Measured Jitter Transfer Characteristic E. Barari, “ Jitter Analysis / Specification, ” May 2002.

63. 63 Measured Jitter Transfer Characteristic E. Barari, “ Jitter Analysis / Specification, ” May 2002.

64. 64 Jitter Generation Intrinsic jitter produced by the PLL –Thermal noise –Drift in VCO Measured at its output –Applying a clear reference signal to PLL –Measuring its output jitter. Usually specified as a peak-to-peak period jitter value

65. 65 Jitter Generation Standard

66. 66 Jitter Generation Measurement Direct measurement of p-p jitter Phase noise measurement Eye diagram and histogram

67. 67 Jitter Generation Measurement

68. 68 Measurement Considerations Calibration Measurement range Measurement time Power Frequency offset

69. 69 TF from Noise in VCO Control Voltage KdKd + v Cn + K VCO /s  LO F(s) Can be viewed as low-pass filter

70. 70 TF from Noise in VCO Control Voltage

71. 71 TF from Phase Noise in VCO KdKd + n+n+ K VCO /s  LO F(s) High-pass filter The same as H e (s)

72. 72 Phase Error in VCO KdKd nn K VCO /s  LO F(s) v Cn dominate at low frequencies  n dominate at high frequencies v Cn  REF+   LO ee H C (s)H  (s)