1. 1 CLEO PAC 11/March/00 M. Selen, University of Illinois CLEO-III Trigger & DAQ Status Trigger Illinois (Cornell) DAQ OSU Caltech Cornell

2. 2 CLEO PAC 11/March/00 M. Selen, University of Illinois Trigger Philosophy  Make a sophisticated Level-1 trigger decision (latency~2.5  s) before invoking readout dead-time.  Make trigger decision every 42ns (i.e. pipeline). CLEO-III Trigger At L = 3 x 10 33 this corresponds to ~250 Hz. Design CLEO-III trigger/DAQ for 1000 Hz max. RF bucket Pipeline clk Early DR Late DR Early CC Late CC look here for CC info 72 MHz 24 MHz look here for DR info Suppose event happens here

3. 3 CLEO PAC 11/March/00 M. Selen, University of Illinois Mixer/Shaper Boards AXTR(16)AXX(16) DR3 Pre-amps STTR(12) TRCR L1LUMI G / CAL DFC DAQ CLEO Analog Gates Contr. Mixer/Shaper Crates (24) TPRO(2) TCTL TIM DM/CTL TIM DM/CTL TIM DM/CTL TPRO(4) TIM DM/CTL TIM DM/CTL AXPR CCGL SURF Drift Chamber Crates Axial tracker Stereo tracker TILE (8) QVME Barrel CC CC Digital Level 1 decision Flow control & Gating L1D Patch panel TILE (8) QVME Barrel CC TILE (8) QVME Endcap CC CLEO-III Trigger: System Inventory

4. 4 CLEO PAC 11/March/00 M. Selen, University of Illinois Example (they all look similar): Level-1 Trigger Decision Board VME/DAQ Interface Trigger LogicCustom BP Trigger Hardware Example

5. 5 CLEO PAC 11/March/00 M. Selen, University of Illinois FPGA based Logic DAQ/ VME Circular Buffer Inputs Outputs TDI TMS TCK TDOJTAG Common Trigger Board Structure

6. 6 CLEO PAC 11/March/00 M. Selen, University of Illinois Stereo (blocks) Axial (all wires) Tracking Trigger (Axial + Stereo)

7. 7 CLEO PAC 11/March/00 M. Selen, University of Illinois #tracks ev-time time 2 track Events Trigger Bucket Finding the Event Time

8. 8 CLEO PAC 11/March/00 M. Selen, University of Illinois Present summing =Tile summing = Simulated Efficiency contained shower Threshold = 500 MeV Energy sharing between boards can result in a loss of efficiency: CC Trigger

9. 9 CLEO PAC 11/March/00 M. Selen, University of Illinois Analog “TILE” Boards

10. 10 CLEO PAC 11/March/00 M. Selen, University of Illinois Barrel (Crate 1 Card 13) Endcap (Crate 21 Card 16) Preliminary Peek at the CC Trigger Data

11. 11 CLEO PAC 11/March/00 M. Selen, University of Illinois 1 m/s crate   CC Tile Processor

12. 12 CLEO PAC 11/March/00 M. Selen, University of Illinois LUT 8 FPGAs Timing (3) Info (185) Timing (TR, CB or CE) Info (valid at timing edge) Route 48 Prescale 24 Bunch 24 Scaler L1- accept Backplane Level 1 Decision

13. 13 CLEO PAC 11/March/00 M. Selen, University of Illinois % Generic Hadron Line, Barrel Timing % SUBDESIGN line0( in[117..0]: INPUT; out: OUTPUT; ) Variable 1cblow: SOFT; 3tracks: SOFT; evtime: SOFT; Begin -- trigger bit mappings: tr_time[1..0]= in[1..0]; cb_time[1..0]= in[3..2]; ce_time[1..0]= in[5..4]; cc_time[1..0]= in[7..6]; tr_n_hi[3..0]= in[11..8]; tr_n_lo[3..0]= in[15..12]; tr_n_ax[3..0]= in[19..16]; tr_lowpos[1..0]= in[21..20]; cb_l_phi[7..0]= in[29..22]; cb_h_phi[7..0]= in[37..30]; cb_low_old[1..0]= in[39..38]; cb_med_old[1..0]= in[41..40]; cb_high_old[1..0]= in[43..42]; ce_low_old[1..0]= in[45..44]; ce_med_old[1..0]= in[47..46]; ce_high_old[1..0]= in[49..48]; cb_n_low[2..0]= in[52..50]; cb_n_med[2..0]= in[55..53]; cb_n_high[2..0]= in[58..56]; ce_n_low[2..0]= in[61..59]; ce_n_med[2..0]= in[64..62]; ce_n_high[2..0]= in[67..65]; bha_theta[7..0]= in[75..68]; cc_spare[15..0]= in[91..76]; cpu_trig[1..0]= in[93..92]; control[23..0]= in[117..94]; ---------------------------------------------- -- trigger line definition 1cblow = cb_n_low[] > 0; 3tracks = (tr_n_hi[]>2) # ((tr_n_hi[]>1)&(tr_n_lo[]>0)) # ((tr_n_hi[]>0)&(tr_n_lo[]>1)) ; evtime = cb_time[0]; out = 1cblow & 3tracks & evtime; End; Writing Trigger Lines

14. 14 CLEO PAC 11/March/00 M. Selen, University of Illinois  All components (except STTR) boards installed and functioning.  Used for collecting engineering run data  Many bugs shaken out (all readout related)  Some minor readout bugs remain, and will be fixed.  Stereo tracking (STTR) boards will be installed by the end of March.  8 of 12 needed boards tested (and working) as of today, the balance (4 + spares) will be shipped to LNS by the end of next week.  Majority of trigger groups effort turning to software development.  Much already exists (readout, sparsification, board debugging & testing, expert online tools).  More user friendly (GUI) code being developed.  Monte Carlo ~90% finished. Trigger Status

15. 15 CLEO PAC 11/March/00 M. Selen, University of Illinois CLEO III DAQ Architecture

16. 16 CLEO PAC 11/March/00 M. Selen, University of Illinois Readout Controller VME PowerPC + VxWorks Fastbus VME-Fastbus Interface (FRITZ) VME CPU Fastbus Interface LUTs

17. 17 CLEO PAC 11/March/00 M. Selen, University of Illinois CLEO III Slow Control Structure CORBA Crates Gas Database HV Magnet Beam Run Control Event Builder Level 3 User Console (Java)

18. 18 CLEO PAC 11/March/00 M. Selen, University of Illinois  All key components installed and functioning.  True for both Data Path & Slow Control  32 PowerPC crate-based CPU’s used “simultaneously” during engineering run!  8 VME crates reading out the 230000 RICH channels.  3 VME crates reading out the trigger system.  2 VME crates reading out the Silicon Vertex System.  4 FASTBUS crates reading out the CC via FRITZ  8 FASTBUS crates reading out the DR via FRITZ.  7 PowerPC’s performed slow control tasks.  Event Builder worked as expected  This is a big deal !  The system will grow slightly for “complete CLEO-III” data-taking in April  1 additional VME crate reading out the stereo trigger.  3 additional VME crates for reading out the silicon.  Stability and “User Friendliness” improving every day. DAQ Status