1. 1 MOS Field-Effect Transistors (MOSFETs)

2. MOSFET ( Voltage Controlled Current Device) MOS Metal Oxide Semiconductor Physical Structure FETField Effect Transistor The current controlled mechanism is based on an electric field established by the voltage applied to the control terminal – GATE Uni-polar Current is conducted by only one carrier IGFETInsulated Gate FET CMOSFETComplementary MOSFET 1930 was Known, 1960s Commercialized 1970s Most commonly used VLSI NMOSFET/PMOSFET n/p-channel enhancement mode MOSFET

3. MOSFET Small Size Manufacturing process is simple Requires comparatively low power Implement digital & analog functions with a fewer resistors very large scale Integrated (VLSI) circuit Study Includes –Physical structure –Operation –Terminal characteristics –Circuit Models –Basic Circuit application

4. Figure 4.1 Physical structure of the enhancement-type NMOS transistor:

5. Device Structure Types“n” channel enhancement MOSFET “p” channel enhancement MOSFET “n” Channel MOSFET –Fabricated on a p-type substance that provides physical support for the device. –Two heavily doped n-type region are created n + Source (‘S’) n + for lightly doped ‘n’ type silicon n+ Drain (‘D’) n + for heavily doped ‘n’ type silicon –Area between source & Drain Thin Layer of Silicon dioxide (SiO 2 ) is grown with thicker of t ox = 2-50 nanometers An excellent electrical insulator Metal is deposited on top of the oxide layer to form the Gate electrode. Metal contact is made to Source & Drain and the substrate (Body)

6. Figure 4.1 Physical structure of the enhancement-type NMOS transistor Cross-section. Typically L = 0.1 to 3  m, W = 0.2 to 100  m, and the thickness of the oxide layer (t ox ) is in the range of 2 to 50 nm.

7. Four terminals –Source (S) –Gate (G) –Drain (D) –Body (B) LLength of channel region WWidth of the substrate t ox Thickener of An oxide Layer Device Structure

8. Metal oxide semiconductor - name is derived from its physical structure Insulted – Gate FET (IGFET) – gate is electrically insulated from the device body –Current in gate terminal is small (10 -15 A) Substrate forms pn junctions with the source & drain region & is kept reversed biased all the time Drain will be at a positive voltage relative to the source, two junctions are at cutoff mode if substrate is connected to the source. Thus Body will have no effect on operation of the device. Device Structure

9. Principle of operation Voltage applied to the Gate controls current flow between Source & Drain with direction from Drain to Source in channel region It is a symmetrical device thus Drain & Source can be interchanged with no change in devices characteristics With no bias gate voltage, two back-to-back diodes exist in series between drain and source. No current flows even if v DS is applied. In fact the path between Source & Drain (10 12 Ω) has very high resistance

10. Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.

11. Creating a Channel for Current Flow Source & Drain are grounded and a positive voltage (v GS ) is applied to the gate. Holes are repelled-leaving behind a carrier depletion-region. Depletion region is populated with the bounded negative charges associated with the acceptor atoms and are uncovered because the neutralizing holes have been push downward into the substrate.

12. Positive gate attracts electrons from the n + source & drain region into the channel region. Due to electrons accumulated under the gate, an ‘n’ region is created & connects source & drain region. Thus if voltage is applied between source & drain, current flows due to mobile electrons between drain & source. ‘n’ region forms a channel – ‘n’ channel MOSET (NMOSFET) Channel for Current Flow

13. An ‘n’ channel MOSFET is formed in a ‘p’ type substrate. Known as “Inversion Layer”. The value of v GS that causes sufficient number of mobile electrons to be accumulate in the channel region to form conducting channel is called threshold Voltage “V t ”. V t for ‘n’ channel is positive & value is 0.5 to 1V Channel for Current Flow

14. Gate & channel region form a parallel plate capacitor, with oxide layer as the capacitor dielectric. Positive charge is accumulated on gate electrode & negative charge on channel electrode. An electric field thus develops in the vertical direction. Capacitor charge controls the current flow through the channel when a voltage v DS is applied. Gate Channel

15. Figure 4.3 An NMOS transistor with v GS > V t and with a small v DS applied. The device acts as a resistance whose value is determined by v GS. Specifically, the channel conductance is proportional to v GS – V t’ and thus i D is proportional to ( v GS – V t ) v DS.

16. Applying a Small v DS v DS is applied (v DS = 50mV) causes i D to flow through induced ‘n’ channel. –Direction is opposite to that of the flow of negative charges. –Magnitude of i D depends upon density of electrons and in term on v GS. v GS ≤ V t –Negligible current i D as the channel has been just induced. v GS > V t –i D current increases, increases conductance of the channel & is proportional to Excess gate voltage (v GS - V t ) – v GS - V t is known as Excess gate Voltage, Effective Voltage Overdrive Voltage (V OV ) –MOSFET operatrates as a linear resistance whose value is controlled by v GS. –v GS above V t enhances the channel – named Enhanced Mode operation & enhanced type MOSFET i D = i S, i G = 0

17. Figure 4.4 The i D – v DS characteristics of the MOSFET When the voltage applied between drain and source, v DS, is kept small. The device operates as a linear resistor whose value is controlled by v GS.

18. Figure 4.5 Operation of the enhancement NMOS transistor as v DS is increased. The induced channel acquires a tapered shape, and its resistance increases as v DS is increased. Here, v GS is kept constant at a value > V t.

19. The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt.

20. Increasing vDS causes the channel to acquire a tapered shape. Eventually, as vDS reaches vGS – Vt’ the channel is pinched off at the drain end. Increasing vDS above vGS – Vt has little effect (theoretically, no effect) on the channel’s shape.

21. Derivation of the iD–vDS characteristic of the NMOS transistor.

22. Drain Current i D Directly Proportional to: –Mobility of Electrons in the channel μ n (μm 2 /V) –Gate Capacitance per unit gate area C ox (μF/ μm) –Width of the substrate (μm) –Gate-Source Voltage v GS (Volts) –Drain-Source Voltage v DS (Volts) Indirectly Proportional to: –Length of the channel (μm)

23. i D – v DS relationship Troide Mode Saturation Mode

24. The p Channel MOSFET Fabricated on an n-type substrate with p+ regions for Drain & Source Holes are the current carriers. v GS & v DS are negative Threshold voltage V t is negative. Both NMOS & PMOS are utilized in Complementary MOS or CMOS circuits

25. Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the p- type body and to the n well; the latter functions as the body terminal for the p-channel device. Complementary MOS or CMOS

26. Modes of operation –Cutoff –Triode (Saturation in BJT) –Saturation ( Active in BJT) i D – v DS Charateristics

27. The iD–vDS characteristics for a device with k’n (W/L) = 1.0 mA/V 2.

28. The iD–vGS characteristic for an enhancement-type NMOS transistor in saturation (Vt = 1 V, k’n W/L = 1.0 mA/V 2 ).

29. Large-signal equivalent-circuit model of an n-channel MOSFET operating in the saturation region.

30. Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by DL). Finite Output Resistance in Saturation

31. Effect of vDS on iD in the saturation region. The MOSFET parameter VA depends on the process technology and, for a given process, is proportional to the channel length L. Finite Output Resistance in Saturation

32. Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance ro. The output resistance models the linear dependence of iD on vDS Finite Output Resistance in Saturation

33. Circuit symbol for the p-channel enhancement-type MOSFET.

34. Characteristics of PMOSFET Triode Mode of Operation

35. Characteristics of PMOSFET Satuaration Mode of Operation

36. The Roll of Substrate : Body Effect Substrate for many Transistors Body is connected to the most negative power supply to maintain cutoff conditions for all the substrates to channel junctions Another gate

37. Temperature Effects V t and K’ n are effected by the temperature V t increases by 2mV per 1 0 C rise in temperature K’ n decreases with rise in temperature thus drain current increases. The effect is dominant. Thus ID decreases with increase in temperature MOSFET in Power circuits

42. Graphical construction to determine the transfer characteristic of the amplifier in (a).

43. Circuit for Example 4.9.

45. Biasing the MOSFET using a large drain-to-gate feedback resistance, RG.

46. Biasing the MOSFET using a constant-current source

47. Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier.

48. Recap : Transfer Function

49. Transfer characteristic showing operation as an amplifier biased at point Q.

50. Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier. The DC BIAS POINT To Ensure Saturation-region Operation

51. Signal Current in Drain Terminal

52. Figure 4.35 Small-signal operation of the enhancement MOSFET amplifier.

53. Total instantaneous voltages vGS and vD

54. Small-signal ‘π’ models for the MOSFET

55. Common Source amplifier circuit Example 4-10

56. Small Signal ‘T’ Model : NMOSFET

57. Small Signal Models ‘T’ Model

58. Single Stage MOS Amplifier

59. Amplifiers Configurations

60. Common Source Amplifier (CS) :Configuration

61. Common Source Amplifier (CS) Most widely used Signal ground or an ac earth is at the source through a bypass capacitor Not to disturb dc bias current & voltages coupling capacitors are used to pass the signal voltages to the input terminal of the amplifier or to the Load Resistance CS circuit is unilateral – –R in does not depend on R L and vice versa

62. Small Signal Hybrid “π” Model (CS)

63. Small Signal Hybrid “π” Model : (CS)

64. Small-signal analysis performed directly on the amplifier circuit with the MOSFET model implicitly utilized.

65. BJT / MOSFET

66. Input Resistance is infinite (R i =∞) Output Resistance = R D Voltage Gain is substantial Common Source Amplifier (CS) Summary

67. Common-source amplifier with a resistance RS in the source lead

68. The Common Source Amplifier with a Source Resistance The ‘T’ Model is preferred, whenever a resistance is connected to the source terminal. r o (output resistance due to Early Effect) is not included, as it would make the amplifier non unilateral & effect of using r o in model would be studied in Chapter ‘6’

69. Small-signal equivalent circuit with ro neglected.

70. Small-signal Analysis.

71. Voltage Gain : CS with RS

72. Source Resistance can be used to control the magnitude of the signal v gs & thus ensure that v gs does not become too large to cause non-linear distortion v gs << 2(V GS -V t ) << 2V OV

73. Common Source Configuration with R s R s causes a negative feedback thus improving the stability of drain current of the circuit but at the cost of voltage gain R s reduces i d by the factor –(1+g m R s ) = Amount of feedback R s is called Source degeneration resistance as it reduces the gain

74. Small-signal equivalent circuit directly on Circuit

75. A common-gate amplifier based on the circuit

76. Common Gate (CG) Amplifier The input signal is applied to the source Output is taken from the drain The gate is formed as a common input & output port. ‘T’ Model is more Convenient r o is neglected

77. A small-signal equivalent circuit

78. A small-signal Analusis : CG

80. Small signal analysis directly on circuit

81. The common-gate amplifier fed with a current-signal input.

82. Summary : CG 4. CG has much higher output Resistance 5. CG is unity current Gain amplifier or a Current Buffer 6. CG has superior High Frequency Response.

83. Common Gate R in in independent of R L & R in = 1/g m & g m in order of mA/V. Input resistance of the CG Amplifier is relatively low (in order of 1kv) than CS Amplifier Loss of signal CG is acts as Unity gain current amplifier current buffer – useful for a Cascade circuitry

84. A common-drain or source-follower amplifier.

85. Small-signal equivalent-circuit model

86. Small-signal Analysis : CD

87. (a) A common-drain or source-follower amplifier :output resistance Rout of the source follower.

88. (a) A common-drain or source-follower amplifier. : Small-signal analysis performed directly on the circuit.

89. Common Source Circuit (CS)

90. Common Source Circuit (CS) With RS

91. Common Gate Circuit (CG) Current Follower

92. Common Drain Circuit (CD) Source Follower

93. Summary & Comparison

94. Quiz No 4 Draw/Write the Following: 27-03-07 BJTMOSFET TypesnpnpnpnMOSpMOS Symbols ‘π’ Model T Model gmgm R e /r s r π /r g

95. Problem 5-44

96. SOLUTION : DC Analysis

97. IE IB g m = 40mA/V

98. Solution Small Signal Analysis

100. Solution Small Signal Analysis : Input Resistance Rin ib + vb -

101. Solution Small Signal Analysis : Output Resistance Itest IEIE I E /(1+ß) I RC R out

102. Solution Small Signal Analysis : Voltage Gain + - + - vi + - veb Vo

103. Solution Small Signal Analysis : Voltage gain + - vi + - veb

104. Solution Small Signal Analysis : Voltage Gain + - vi

105. Solution Small Signal Analysis : Voltage Gain

106. + - + - vi Vo

107. Problem

108. Small Signal Model MOSFET : CD

109. Solution Small Signal Analysis 1/gm gmvsg D

110. 1/gm gmvsg D Solution Small Signal Analysis : Input Resistance Rin Ig=0

111. 1/gm gmvsg D Solution Small Signal Analysis : Output Resistance Itest ID IG=0 IRD Rout Vtest 0 V

112. 1/gm gmvsg D Solution Small Signal Analysis : Voltage Gain + - + - vi + - vsg vo

113. 1/gm gmvsg D Solution Small Signal Analysis : Voltage gain + - vi + - vsg

114. 1/gm gmvsg D Solution Small Signal Analysis : Voltage Gain + - vi

115. Solution Small Signal Analysis : Voltage Gain

116. 1/gm gmvsg D Solution Small Signal Analysis : Voltage Gain + - + - vi

117. Solution Small Signal Analysis

118. Common Emitter –Common Base (CE-CB) Common Emitter –Common Collector (CE-CC) Common Collector - Common Emitter –(CC-CE) Common Collector - Common Base – (CC-CB) Transistor Pairings Amplifiers

119. Problem 6-127(e)

120. DC Analysis 6-127(e)

121. Small Signal Model

123. Rin

124. Small Signal Model Rout + vbe1 - + vbe2 -

125. Small Signal Model

126. Problem6-127(f) Replacing BJT with MOSFET

127. Small Signal Model

129. Rin Rout

131. Problem 6-127(f)

132. Solution P6-127(f) + + - - vbe2 veb1

133. + + - - vbe2 veb1 + vi - Solution P6-127(f)

134. Problem 6-127(f) with MOSFET

135. - - vgs2 vsg1 + + Solution P6-127(f)

136. - - vgs2 vsg1 + + Solution P6-127(f) + vi - i g1 =0

137. Comparison BJT/MOSFET Cct

138. Figure P6.123 Problem 6-123 VBE=0.7 V β =200 K’n(W/L)=2mA/V2 Vt=1V

139. Figure P6.123 DC Analysis

140. VBE=0.7 V β =200 K’n(W/L)=2mA/V2 Vt1=1V Vt2=25mV 0.7V I=0.7/6.8=0.1mA I G =0 2V 1mA

141. Small Signal Model

143. Small Signal Model : Voltage Gain i g =0 + vivi - + v be2 -

144. Small Signal Model : Input Resistance R in + vi - ii i g =0

145. + vivi - R out V test = v o I test IRG Small Signal Model : Output Resistance

146. The Miller Theorem.

147. The Miller equivalent circuit.

148. Miller Theorem

149. Miller theorem Miller theorem states that impedance Z can be replaced by two impedances: Z1 connected between node 1 and ground and Z2 connected between node 2 and ground where

150. Miller equivalent circuit is valid only as long as the rest of the circuit remains unchanged Miller equivalent circuit cannot be used directly to determine the output resistance of an amplifier. It is due to the fact for output impedance test source is required and thus circuit has a major change. Miller theorem

151. Circuit for Example 6.7.

153. Example K=-100 V/V, Z = 1 M Ω

154. OBSERVATIONS The Miller replacement for a negative feedback results in a smaller resistance [by a factor of (1-K)] at the input. The multiplication of a feedback impedance by a factor (1-k) is referred as Miller Multiplication or Miller Effect

155. Small Signal Model CE with R E includng r 0

156. A CE amplifier with emitter degeneration : Input Resistance 1 2 3 4 5 6 7

158. Figure 6.49 A CE amplifier with emitter degeneration to determine A v o. Open Circuit Voltage Gain

159. A CE amplifier with emitter degeneration to determine Output Resistance 1 2 3 4 5 6 7

160. A CE amplifier with emitter degeneration to determine Short-Circuit Trans-conductance Gm

161. Figure 6.33 Active-loaded common-base amplifier

162. Figure 6.33 Active-loaded common-base amplifier to determine Input Resistance 1 2 3 45 6 7

163. Figure 6.33 Active-loaded common-base amplifier With output open-circuit 1 2 8 3 4 5 6 7

164. A CB amplifier to determine Output Resistance 1 2 3 4 5 6 7

165. Quiz No 8 DE 28 EE

166. Quiz No 8 DE 28 EE