1. GOOD MORNING

2. TECHNOLOGY THAT IS DRIVING THE WORLD VLSI AND ASIC DESIGN
VERY LARGE SCALE INTEGRATED
CIRCUIT AND
APPLICATION SPECIFIC INTEGRATED CIRCUIT DESIGN
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3. DEVELOPMENT IN INTEGRATED CIRCUIT TECHNOLOGY
SMALL SCALE INTEGRATION
SSI
< 10 TRANSISTORS
10 TO 100 TRANSISTORS
MEDIUM SCALE INTEGRATION
MSI
LARGE SCALE INTEGRATION
LSI
100 TO 1,000
TRANSISTORS
VERY LARGE SCALE INTEGRATION
VLSI
MORE THAN 1000 TO MILLION
OF TRANSISTORS
ULTRA VLSI
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4. VLSI DESIGN CYCLE Design specification HDL CAPTURE RTL SIMULATION
NETLIST GENERATION
IMPLEMENTATION
IN FPGA
PLACEMENT,ROUTING
POSTLAYOUT
SIMULATION,MASKING
PACKAGING
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5. VLSI DESIGN DOMAINS ALGORITHM PROCESSORS DATA PATH; ALU,REGISTERS
Behavioral
Structural
Physical 1 2 3
ALGORITHM
PROCESSORS
DATA PATH; ALU,REGISTERS
RTL (HDL)
LOGIC
TRANSISTOR
TRANSISTOR
CELL.
CHIP,MODULE
BOARD,SYSTEM
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6. HDL incorporates timing feature to represent real hardware.
Introduction to HDL
Hardware descriptive languages are used purely to describe the digital circuits in various level of abstraction ranging from gate to board and system level.
HDL differs from conventional HLL in the sense they make use of concurrency however sequential option is also provided.
HDL incorporates timing feature to represent real hardware.
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7. AND GATE C<=A AND B after propagation delay; A C Some delay occurs
To pass the input
Signal at the output A C B
C<=A AND B after propagation delay;
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8. Transistor representation of And gate
Delay occurs due to RC effect of the transistor.
VDD C B A
Acts as a capacitor
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9. Placement TYPE1
Cell A
Cell C
Cell B
Cell D
Cell E
Cell F
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10. PLACEMENT TYPE2
Cell B
Cell F
Cell A
Cell C
Cell D
Cell E
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11. ROUTING
Cell A
Cell C
Cell B
Cell D
Cell F
Cell E
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12. Nmos transistor
gate
source
Drain
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13. FABRICATION OF NMOS TRANSISTOR
BASE SILICON
SIO2 ADDED AT THE TOP
PHOTOMASKING AND
UV RAYS
Polysilicon and diffusion
To create base source and drain region
Metaliziation
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14. IMPORTANT PARAMETERS TO BE CONSIDERED WHILE DESIGINING THE CHIP.
1. POWER
2.SPEED
3.AREA
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15. EXAMPLE
FULL ADDER
FULL ADDER A
CARRYOUT B
SUM
CIN
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16. TRUTH TABLE A B CIN SUM CARRYOUT Sum<= A XOR B XOR CIN ;
Sum<= A XOR B XOR CIN ;
Carry<= (A AND B) OR ( A AND CIN) OR (B AND CIN) ;
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17. VHDL DESCRIPTION library IEEE; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fulladder1 is
Port ( a : in std_logic;
b : in std_logic;
cin : in std_logic;
CARRYout : out std_logic;
SUM : out std_logic);
end fulladder1;
architecture Behavioral of fulladder1 is
begin
SUM<=a xor b xor cin;
CARRYOUT<=(a and b )or (a and cin) or (b and cin);
end Behavioral;
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18. SIMULATION WAVE
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19. LIST TABLE
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20. RTL SCHEMETIC
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21. SYNTHESIS
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22. © R.Lamsal