1. Advantages of Using CMOS
Compact (shared diffusion regions)
Very low static power dissipation
High noise margin (nearly ideal inverter voltage transfer characteristic)
Very well modeled and characterized
Mechanically robust
Lends itself very well to high integration levels
“Analog” CMOS process usually includes non-salicided poly layer for linear resistors.
SiGe BiCMOS is very useful but is a generation behind currently available standard CMOS
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

2. Transistor fT Calculation
VDD id
fT is the frequency at which becomes 1. ig
vgs
Cgs
Universities generally don’t have access to more modern processes.
VGS
fT gives a fundamental speed measure of a technology.
0.25 µm CMOS: fT ~ 23GHz (VDD = 2.5V)
0.18 µmCMOS: fT ~ 57GHz (VDD = 1.8V)
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

3. Static CMOS propagation delay:
Vin
Vout
Assume: Wp = 3Wn for optimum noise margin.
Lp = Ln = Lmin
This simple exercise gives insight into how omega_T affects actual circuit operation, as well as the speed limitations of standard CMOS gates.
Operation is 4X slower than theoretical maximum due to n-channel & p-channel gates connected in parallel.
(Actual  values will be higher due to high diffusion capacitances present in sub-micron transistors.)
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

4. Verifying with simulation:
n-channel ac simulation
to determine fT:
CMOS inverter transient simulation: IG
Vout
Vin ID
fT = 57GHz
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

5. Single-Ended Signaling in CMOS
VDD
Vin
Vout
ISS
IDD
IDD
Vin
Vout
sub
ISS
VSS
Series R & L cause supply/ground bounce.
Resulting modulation of transistor Vt’s result in pattern-dependent jitter.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

6. Effect of Supply/Ground Bounce on Jitter
data in
clock in
clock out
data out
Rs = 5 Ls = 5nH
clock out
Rs = 0
Ls = 0
clock out
Rs = 5
Ls = 5nH
data out
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

7. Summary of CMOS Gate Performance
Simple & straightforward design.
Robust operation.
Nearly zero static power dissipation.
Advantages of static CMOS gates:
Full speed of transistors not exploited due to n-channel & p-channel gate in parallel at load.
Single-ended operation causes current spikes leading to VDD/VSS bounce.
Single-ended operation also highly sensitive to VDD/VSS bounce leading to jitter.
Disdvantages of static CMOS gates:
Jitter properties of static CMOS even more serious than speed limitations.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

8. Current-Mode Logic (CML)
CML inverter:
VDD
Vin+
Vin-
Vout-
Vout+
ISS R CL
Based on conventional differential pair
Differential operation
Inherent common-mode rejection
Very robust in the presence of common-
mode disturbances (e.g., VDD / VSS bounce)
This structure is conventionally used as a simple amplifier for small signals. In logic circuits, full switching is utilized.
Conceptually, the operation is simple, but it’s worthwhile to analyze various aspects in depth to see operation can be optimized.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

9. DC Biasing of CML Inverter
VDD + + R R _ _
To keep current source transistor in saturation:
We’ll assume output connects directly to input of identical gate. (Source followers generally not used in CMOS.) + VS + _ _
VGS
VGS
ISS
VBIAS
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

10. Logic Swing & Gain of CML Inverter
VDD R R
VDD-ISSR
VDD
ISS
We’re assuming square-law behavior for now for simplicity. Although this is a poor approximation for sub-micron devices, we still gain insights. Will verify with simulation later.
To achieve full current switching: CL CL
VDD
VDD-ISSR
ISS
for correct operation
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

11. Small-Signal Behavior of CML Inverter
Small-signal voltage gain:
(Assuming fanout of 1)
rise/fall time constant:
Recall
for full switching
Note: rising & falling
time constants are the same
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

12. Speed vs. Gain in Logic Circuits
fast input transition:
step response determined by 
This distinction is especially important in SerDes because there exist data & clock signals at a number of different bit rates/frequencies.
slow input transition:
step response determined by Av
Largest possible gain-bandwidth product is desirable.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

13. Relationship between Av ,  , and Vswing
“large-signal” gain-bandwidth product
Larger logic swing preferred for higher gain-bandwidth product
Larger Vswing  Larger Vmin  smaller W/L  larger current density
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

14. Thought Experiment Slower!
ISS
ISS
Suppose we decrease current density by increasing W/L:
Slower!
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

15. Note that the load is only one gate capacitance:
CML speed ~ 2.5 times faster than static CMOS
n-channel ac simulation
to determine fT:
CML buffer transient simulation: IG ID
fT = 57GHz
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

16. Should be large enough to allow sufficient gain-bandwidth product.
Typical Vswing:
Should be large enough to allow sufficient gain-bandwidth product.
Should be small enough to prevent transistors from going into triode.
* CML will still work in triode (unlike BJT), but there is no additional
speed benefit.
Once Vswing has been chosen, designer can trade off between gain & bandwidth by parameterizing between R & ISS:
Higher speed: ISS R
Higher gain: ISS R
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

17. Other Benefits of CML Gates
Constant current bias  VDD / VSS bounce greatly reduced
ISS
KCL sets this current to be nearly constant.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

18. Rs = 5 Ls = 5nH Rs = 0 Ls = 0 Rs = 5 Ls = 5nH clock out clock out
data in
data out
clock in
clock out
Rs = 5 Ls = 5nH
clock out
Rs = 0
Ls = 0
clock out
Rs = 5
Ls = 5nH
data out
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

19. Non-inverting buffer available without additional delay:
CMOS: tp
2tp
inverter
buffer
CML:
inverter
buffer
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

20. Fanout & Scaling of CML GatesR R
Vout-
Vout+ 1x =
Vin+
Vin-
ISS
R/n
R/n
Vout-
Vout+ nx
All voltages unchanged from unit-sized buffer.
Currents & power increase by factor of n. =
Vin+
Vin-
nISS
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

21. increases linearly with fanout.
For fanout of n:
increases linearly with fanout.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

22. degradation due to interconnect capacitance to minimize
From interconnect, etc.; assumed not to scale with buffer sizes
Should set
degradation due to interconnect capacitance
to minimize
Power (proportional to n) determined primarily by interconnect capacitance!
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

23. CML buffer design procedure:
Sub-micron MOSFETs obey square-law characteristics only in a limited region! + _
VGS
Mobility reduction (linear)
Square-law behavior
Weak inversion (exponential)
VGS
CML buffer design procedure:
Determine largest allowable ISS (usually limited by electromigration constraints)
Choose “unit-sized” n-channel transistor (typically W/L=20)
Run a series of simulations to determine optimum value of R:
R too small: full current switching not achieved
R too large: slower than necessary
Choose minimum scaling factor after laying out some test buffers of various sizes and determining approximate value of interconnect capacitance Cp.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

24. 1. Determine largest allowable ISS
standard layout
shared drain
(1/2 diffusion capacitance)
Imax independent of W
determined by electromigration limits
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

25. CML Design Procedure Example
ISSR = 360mV
tp = 10ps
R too small
Choose:
R = 1200
ISSR = 480mV
tp = 12ps
*R optimum*
R = 1500
ISSR = 600mV
tp = 14ps
R too large
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

26. Parameterizing Between Gain & Bandwidth
ISS = 100 µA
R = 4.8 k
Av = 9.3 dB
BW = 2.6 GHz
ISS = 200 µA
R = 2.4 k
Av = 7.1 dB
BW = 5.5 GHz
ISS = 400 µA
R = 1.2 k
Av = 3.9 dB
BW = 11.5 GHz
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

27. Parameterized CML Buffer
GSCALE: Global scaling parameter
(depends on Cp)
MSCALE: Local scaling parameter
(depends on fanout or bit rate)
GBW: Gain-bandwidth parameter
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

28. CML with p-channel Active Load
Can be used if linear resistors are not available.
p-channel load transistors operates in triode region:
Increased capacitance and mismatch result
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

29. Capacitance Comparison (1)
Poly resistor:
p-channel MOSFET:
gate
sub
channel
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

30. Capacitance Comparison (2)
(Numbers based on TSMC 180nm CMOS process)
Cpoly-sub  Cchannel-sub : fF/m2
Cdepletion : fF/m2
Cchannel-gate : fF/m2
Poly resistor:
Wpoly = 0.6
Lpoly = 2.5
= 0.1 fF
p-channel MOSFET:
Wchannel = Wdiff = 2.5 µm
Lchannel = 0.18 µm
Ldiff = 0.3 µm
= 0.9 fF fF fF = fF
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

31. Capacitance Comparison (3)
R = 1.2 k
s = 235 
Wr = 0.6 µm
Lr = 2.5 µm
Cres = 0.1 fF
Wp = 2.5 µm
Ldiff = 0.3 µm
Cd2 = 2.8 fF M2 M2 M1 M1 M1 M1
Cd1 = 3.7 fF
Cg1 = 5.8 fF
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

32. Pulse Response Comparison PWin = 100ps
resistor load
R = 1.2 k
td = 16 ps; PWout = 100 ps
p-channel load
(W/L)p = 2.5 µm / 0.18 µm
td = 20 ps; PWout = 98 ps
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

33. Eye Diagram Comparison including mismatch effects
resistor load
= 1.5% mismatch
p-channel load
= 4% mismatch
160mV gate-referred mismatch
DCD
ISI
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

34. Series-Gated CML TopologyMA MB
XOR gate:
Back to conventional CML
Common-mode voltage of BP/N critical:
Too low  current source transistor biased in triode
Too high  Transistors MB biased in triode
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

35. Series-Gated CML (2) BP BN Transistors should be biased in saturationVS I1 I2 BP BN
ISS
Transistors should be biased in saturation
to realize maximum gm .
Especially important when gate voltages exhibit
slow slew rates
Slope = gm
-ISS
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

36. DC current: Transient response: (400mV amplitude sine
VB(cm) = 1.0
VB(cm) = 1.3
VB(cm) = 1.6
DC current:
VB(cm) = 1.3
VB(cm) = 1.0
Transient response:
(400mV amplitude sine
wave applied to BP/BN)
VB(cm) = 1.6 t
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

37. Level-Shifting CML Buffer
Used to drive clock inputs of series-gated CML gates
VDD
Rcm
ISS R + _
Output levels:
DC levels shifted down by ISSRcm
Vswing unchanged
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

38. CML Select Circuit
Be reassigning the inputs, the XOR can be transformed into a Select circuit. Used in a 2:1 multiplexer.
ISS R AP AN BP BN
SELA
SELB
OUTP
OUTN
SELA
Consider setting B = OUT
AP/N
BP/N
OUTP/N
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

39. CML Latch By setting BP/N = OUTP/N, we can construct a CML latch: ISSDP DN
OUTP
OUTN
CKP
CKN
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

40. CML D Flip-Flop CKP/N Output OUTP/N is synchronized withDP DN
CKP
CKN XN XP
OUTN
OUTP
Discuss clock-to-q delay vs. d-to-q delay. Reinforce metstable behavior.
CKP/N
DP/N
OUTP/N
Output OUTP/N is synchronized with
CKP/N falling edge.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

41. CML Latch Design Considerations
IGG
IGG
VGG R
slope=1/rgg
VGG
With standard CMOS we usually don’t need to consider this because of the inherent high gain.
dc operating points
Necessary criterion for bistability:
at middle operating point
(Equivalent to loop gain = gmR > 1)
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

42. Avoiding Latch Transparency
As shown in previous slide, logic levels at latching can vary depending on circuit parameters. Could lead to latch transparency.
XP/N
“transparent” latch
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

43. GBW parameter can be increased to ensure bistability. R=1000 R=800XP XN XP XN
GBW parameter
can be increased to
ensure bistability.
R=1000
R=800
R=600
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

44. Buffering Clock Signals (1)
Clock signals (generated from VCO or clock divider) often drive large capacitive loads. 1x 1x C … n 1x C C
Fanout = n
For a large fanout, attenuation of clock amplitude will occur.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

45. Buffering Clock Signals (2)
ktp
n x
k2 x
k x … 1x
m stages
Now  is increased by k << n
less attenuation at each stage
Delay = mktp
Power = P1(1 + k + k2 + … + n)
Power dissipated by first stage
As fclock  1/tp then k  1; number of stages and total power become very large.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

46. Buffering Clock Signals (3)
Since clock signal is made up of a single frequency (+ harmonics),
resonance can be used to increase gain with greatly reduced power dissipation.
Resonant frequency:
at resonance
If lossless inductors were available, we could achieve high gain at any frequency
simply by choosing the correct inductor value.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

47. On-Chip Passive Elements
Resistor: t w l
Capacitor: l
(+ fringing) w d
substrate l
Inductor:
pH/m l t w
Inductance calculation much more complicated!
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

48. l l pH/m w Special case of Greenhouse result
Note for l >> w, L is a weak function of w
To increase effective inductance per unit length, we make use of
mutual inductance via spiral structure:
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

49. Modeling of Spiral Inductor
Accurate lumped model should include:
Series inductance (self + mutual) & resistance
Skin effect (frequency dependent series resistance)
Interwinding capacitance
Capacitance to substrate
Substrate capacitance & loss 1 2
number of turns n = 2
Procedure for constructing lumped model:
2-port s-parameters over frequency range of interest
(this comes from the inductor simulator)
Choose lumped circuit topology.
Run simulations to find the optimal lumped circuit
element values such that the the circuit s-parameters
are sufficiently close to the inductor’s s-parameters
(can use .net and .optimize in HSPICE)
Design of inductor requires:
inductor simulation package
(e.g., asitic)
trial and error
conversion to lumped element model
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

50. Modeling of Spiral Inductor (cont.)
Link to “asitic” web pages:
Inductor magnitude impedance vs. frequency
Parameters most relevant to circuit designers:
Inductance
Series resistance
Self-resonant frequency
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

51. Modeling of Spiral Inductor (cont.)
Cint L Rs
Cox2
Cox1
Csub1
Csub2
Rsub1
Rsub2 1 2 1 2
It’s now very common for foundries to provide convenient, parameterized L models, usually taken from on-chip measurements. It’s important to find out the frequency range of the measurements. If not sufficient, it’s worthwhile to develop one’s one models using various tools (ADS, etc.) L:
Rs:
Cint:
Cox:
Csub/Rsub:
Self/mutual inductance
Series resistance
Interwinding capacitance
Oxide capacitance
Substrate capacitance/resistance
Values of L and Rs in lumped model should correlate with physical parameters.
Values of other lumped model elements need not necessarily correlate with physical parameters.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

52. Series Rs has more important effect:
Parasitic capacitances usually combine with load capacitance  L should be decreased slightly
Series Rs has more important effect: R’ C L' L C R Rs
At resonance, Im [Y(jr)] = 0:
Slight increase in effective inductance
Very important effect!
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

53. CML Tuned Amplifiers (1)
Sets common-mode
output voltage
Differential-mode ground
CL resonates out with L
Gain at resonant frequency = gm R’
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

54. CML Tuned Amplifiers (2)
Symmetric inductor structure can be used:
Single structure allows more inductance to
be realized from mutual coupling
 less series resistance
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

55. CML Tuned Amplifiers (3)
Higher-gain topology:
Gain is much higher at resonance, but depends completely on Rs.
Variation in gain correlates with variation in metal (not resistor) sheet resistance.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

56. CML Tuned Amplifiers (4)
Watch out for ac current amplitude in inductors!
Iin R’ C L’ + IL
Vswing _
Let Vswing = 500mV, L=0.5nH, f =10GHz:
Spiral inductor should be wide enough
to meet ac electromigration specs.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

57. Inductors in Broadband Circuits
LC lossless transmission line (Z0) R + R
Vout
Vin _
For a given capacitor, this example shows that series inductors can increase the bandwidth at the expense of additional delay.
0.5
0.5    
slope = -Td
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

58. Series Peaking (1) “Series peaking”
With direct connection of 2 buffers,
output & input capacitances are in parallel: Cd Cg
Lser value would be chosen according to max. BW which would correspond to impedance matching.
More examples of this technique will be shown later.
By connecting an inductor between the capacitors, the bandwidth and delay increase: Cd Cg
Lser
“Series peaking”
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

59. Series Peaking (2) R Using set Vx- Vx+
Series peaking provides speed at the expense of extra delay.
Lser
Vin+
Vin- Cd Cg
Cd = Cg = 16 fF
R = 400 W
Lser = 0
BW = 6.3 GHz
Lser = 3.5 nH
BW = 8.3 GHz
Frequency response:
Vin
Vx (Lser = 0)
Transient response:
Vx (Lser = 3.5 nH)
Vin
Vx (Lser = 0)
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

60. Shunt-Peaking (1)
By connecting an inductor in series with the load resistor (series connection in shunt with output), more current is used, for a longer time, to charge the load capacitance.
As distinct from series peaking, shunt peaking places inductor in series with load resistor (shunting CL).
Idea behind this technique is that L opposes current change in R branch, allowing more time for C to charge with full current.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

61. Properties of Shunt-Peaking
Frequency response: CL
Insertion of shunt-peaking inductor introduces a zero, partially cancelling the existing pole, and a higher-frequency pole, thus broadbanding the circuit.
Even though there is an inductor, it is not a frequency-selective circuit; thus resonance is not desired here.
Resonant frequency: X
Re s
Im s
L = 0:
pole at s = −1/RC X O
L ≠ 0:
zero at s = −R/L
additional pole at
s ≈ −(1/CR + R/L)
No resonance for
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

62. Shunt-Peaking -- AC Response
BW = 6.3 GHz
L = 1.8 nH
BW = 9.4 GHz
L = 3.7 nH
BW = 14.3 GHz
Use of shunt-peaking
increases small-signal bandwidth
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

63. Shunt Peaking − Transient Response
Step Response:
td = 13.4 ps
L = 1.8 nH
td = 8.5 ps
L = 3.7 nH
td = 6.7 ps
Pulse Response (Dtin = 50 ps):
L = 3.7 nH
Dtout = 50.8 ps
ISI = 16 mUI
L = 1.8 nH
Dtout = 50.0 ps
ISI = 0 mUI
L = 0
Dtout = 48.7 ps
ISI = 26 mUI
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

64. Shunt Peaking – ISI vs. Pulse Width
ISI (UI)
Input pulse width
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

65. Other Advantages of Shunt-Peaking
CML load is passive & linear
Can be shown to be very robust in the presence of parasitic series resistance and shunt capacitance  inductors can be placed far away from other CML circuit elements.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

66. Effect of Shunt-Peaking Inductor Parasitics (1)L L L CP CP L
long metal lines RP RP R R R R CL CL CL CL
Series resistance RP simply adds to R
Shunt capacitance CP resonates with L …
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

67. Effect of Shunt-Peaking Inductor Parasitics (2)
ISI (UI)
Moderate amount of parasitic capacitance
has similar effect to slightly larger inductor.
Input pulse width
ISI (UI)
Disadvantages of using passive inductors:
Consume huge die area
Difficult to design & model
Input pulse width
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

68. Multi-layer Inductors (1)
metal 6
metal 6 d
metal 5
metal 5 d
Distance d between two metal layers is much smaller than lateral distances (e.g., w, l, s)
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

69. Multi-layer Inductors (2)
2-port representation of coupled inductors:
series connection of coupled inductors: L1 L2 i1 i2 M 1 + _ 2 i1 i2 + + 1 L1 L2 2 _ _
Passivity constraint:
For metal geometries close to each other,
k is close to unity.
For L1 = L2 = L, we have:
In general, for n layers we have:
Multi-layer inductors are more appropriate for shunt-peaking than resonant structures due to additional contact resistance.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

70. Multi-layer Inductors (3)
Effective Capacitance: Ci Cj
For more details, see:
A. Zolfaghari, A. Chan & B. Razavi, “Stacked inductors and transformers in CMOS technology,”
IEEE Journal of Solid-State Circuits, vol. 36, April 2001, pp
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

71. Multi-layer Inductors (4)
Area comparison:
metal 6 over metal 4
46 x 46
w = 4; s = 2; n = 2.5
L=2.0 nH
R=12.5 
metal 6 only
100 x 100
w = 4; s = 2; n = 4
L=2.0 nH
R=6.9  +
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

72. Active Inductors (1) Rgyr Rgyr i1 i2 iin v1 v2 vin C
Impedance inversion:
Ideal gyrator:
Rgyr
Rgyr i1 i2
iin + + + v1 v2
vin C _ _ _
Matrix representation (Z-parameters):
Port 1 exhibits inductance when
port 2 is connected to a capacitance.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

73. Active Inductors (2) Consider common-drain configuration: RG
i1 applied with port 2 open-circuited: i2
i2 applied with port 1 open-circuited: + RG v2 _ _
(Assume RG gm > 1) v1 i1 +
Complete Z-parameters (lossy/active gyrator):
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

74. Active Inductors (3) vin Interpretation of non-ideal matrix entries: +_
vin
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

75. Active Inductors (4) At low frequencies (Cgs open)  Zsource = 1/gm
Impedance at port 1 with port 2 terminated with transistor Cgs:
At low frequencies (Cgs open)  Zsource = 1/gm
At high frequencies (Cgs short)  Zsource = RG
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

76. Active Inductors (5) vin + _ Equivalent circuit:
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

77. CML Buffer with Active Inductor Load
Low-frequency gain:
For shunt peaking:
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

78. Active Inductor AC Response
RG = 4k
RG = 2k
RG = 0
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

79. Active Inductor Transient Response (1)
Differential signals:
RG = 0
PW = 97ps
RG = 5k
PW = 100 ps
RG = 10k
PW = 104 ps
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

80. Active Inductor Transient Response (2)
Single-ended signals:
Problem: n-channel load shifts output by Vt.
Vsb > 0; body effects exacerbates this effect..
Single-ended
input
Single-ended
outputs
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine

81. Active Inductor Alternate Topology
p-channel load exhibits lower Vt
(Vbs = 0)
differential
single-ended
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine