Presentation is loading. Please wait.

Presentation is loading. Please wait.

CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy CAD Tools for 3D-IC and TSV-based designs Kholdoun TORKI

Published byLilian Carter Modified over 9 years ago

Similar presentations

Presentation on theme: "CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy CAD Tools for 3D-IC and TSV-based designs Kholdoun TORKI"— Presentation transcript:

1 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy CAD Tools for 3D-IC and TSV-based designs Kholdoun TORKI Kholdoun.Torki@imag.fr CMP 46, Avenue Félix Viallet, 38031 Grenoble, France http://cmp.imag.fr

2 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy Agenda Introduction Process overview 3D-IC Design Platform 3D-IC industrial CAD tools Conclusion

3 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy SiP versus 3D-IC

4 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy Tezzaron Process Flow for TSV and DBI (using Via Middle process) Starting wafer in 130nm (5 Cu metal layers + 6 th Cu metal as DBI) Source Tezzaron

5 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy Top Tier (10um thickness) Bottom Tier (Handle wafer) Resulting 2-tier 3D-IC integration TSV and DBI (Via Middle Process) Bond pad for wire bonding or bump, flip-chip … Source Tezzaron

6 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy Interconnection Type Line Width (µm) Line Thickness (µm) Line Resistance (Ohm/cm) Max Length (cm) Direct Bond Interface (DBI)2-100 00 Through Si Via (TSV)1-100 500-10005-100 On-Chip0.1-2 100-10000.1-1.5 Thin-film10-255-81.25-420-45 Ceramic75-10016-250.4-0.720-50 PCB60-10030-500.06-0.0840-70 Shielded Cables100-45035-4500.0013-0.033150-500 Interconnections SizeCapacitanceSeries Resistance DBI2µ<<< TSV1. 2µ2-3 fF<1.5 Ω Interconnections in the 3 rd dimension at Tezzaron/GF 130nm

7 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy The more is the Design Automation on the 3 rd dimension, the more is the 3D-IC Integration. 2 D 2.5 D Memory Stack Simple Imaging Sensor Pixel Sensor (HEP) Multi-Processors + Memory NoC 3 D Processor + DRAM + RF + MEMS + Optical communication Design Methodology System Complexity

8 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy 3D-IC Design Platform

9 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy Tezzaron / GlobalFoundries Design Platform Modular Design Platform. It has all features for full-custom design or semi- custom automatic design. PDK : Original PDK from GF + (TSV / DBI) definition from Tezzaron Libraries : CORE and IO standard libraries from ARM Memory compilers : SPRAM, DPRAM and ROM from ARM 3D-IC Utilities : Contributions developments embedded in the platform Tutorials, User’s setup. All modules inside the platform refer to a unique variable, making it portable to any site. The installation procedure is straightforward. Support of CDB and OpenAccess databases.

10 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy assura calibre cds_cdb cds_oa doc eldo hercules hspice prep3DLVS skill spectre strmMaptables_ARM strmMaptables_Encounter chrt13lprf_DK009_Rev_1D (Version issued in Q1 2011) calibre: 3DDRC 3DLVS DRC FILLDRC calibreSwitchDef assura: FILLDRC LVS QRC hercules: DRC LVS STAR_RCXT PDK Tezzaron / GlobalFoundries

11 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy  DBI (direct bonding interface) cells library. (FermiLab)  3D Pad template compatible with the ARM IO lib. (IPHC)  Preprocessor for 3D LVS / Calibre (NCSU)  Skill program to generate an array of labels (IPHC)  Calibre 3D DRC (Univ. of Bonn)  Dummies filling generator under Assura (CMP)  Basic logic cells and IO pads (FermiLab)  Floor-planning / automatic Place & Route using DBIs, and TSVs (CMP)  Skill program generating automatically sealrings and scribes (FermiLab)  MicroMagic PDK (Tezzaron/NCSU) Collaborative Work on the Design Platform HEP labs contributing with Programs, Libraries, and Utilities. All included in the Design Platform

12 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy Virtuoso Layout Editor with 3D layers and verification TSV Back Metal Back Pad DBI Assura Calibre Virtuoso from Cadence IC 5.1.41

13 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy Virtuoso from Cadence IC 6.1.4 Customized Menu with some utilities

14 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy Libraries from Providers and Users ARM GF/TSC FermiLab IPHC Univ. Bonn NCSU

15 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy Virtuoso / Calibre DRC Interactive Menu Setting switches graphically

16 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy Choosing 2D or 3D LVS Virtuoso / Calibre LVS Interactive Menu

17 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy 3D viewer in Virtuoso Layout - Graphically Interfaced into Virtuoso. - Works for both CDB and OA. - Use a free and open-source VRML viewer.

18 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy IPHC Contribution for 3D-IC IO Libraries Pad shell containing TSV and DBI allowing the use of the ARM IO libraries in 3D-IC designs

19 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy IPHC Contribution for 3D-IC IO Libraries Pad shell containing TSV and DBI allowing using the ARM IO libraries in 3D-IC designs

20 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy IPHC Contribution for 3D-IC IO Libraries Pad shell containing DBI and TSV connecting the pad to the backside bonding pad

21 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy 3D-IC Automatic P&R using DBI and TSV 3D Floor-Planning DBI, TSV, IO placement System Level Partitioning Automatic Place & Route Extraction, Timing Analysis Physical verification 3D DRC, 3D LVS Dummies Filling Final 3D DRC Design exploration at system level Design exploration at the physical level DBI, TSV, and IO placement & optimization Cells and blocks place & route can be done tier by tier To be done for each tier, then combined for back-annotation to the 3D top level system Similar to the full-custom design flow

22 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy Automatic Place & Route with Direct Bond Interface - Custom scripts allowing routing pins on DBIs. - The resulting layout is compliant to the Tezzaron DRC, LVS etc … DBI completely routed down to the lower metal layer DBI array generation + P&R

23 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy Saving the floor plan for the bottom tier, and apply it for top tier. Place & Route taking into account the locations of the DBIs. The place & route for both tiers is optimal for timing, buffer sizing and power performance. This results in a “correct-by-construction” design. Automatic P&R with Direct Bond Interface

24 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy Cadence / Encounter Bump Array Generator

25 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy Cadence / Encounter Signal Bumps Assignment

26 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy Before After Custom Scripts Enabling Routing on DBIs Placing logical pins on bumps (DBIs), and extract their location. Generating Physical pins from these locations. They can now be used as terminals for routing.

27 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy - DBIs Placement - TSVs Placement - Obstructions on TSVs - Std cells Placement - Clock Tree Synthesis Filler Cells Placement - Clock routing - Final routing Automatic P & R Design Flow (From Floor-Plan to Routed Design)

28 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy Clock and all nets routing is enabled on M1-M5

29 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy Cadence is making its 3D-IC design tools available to selected European academic institutions in partnership with the Europractice scheme operated by the UK Science and Technology Facilities Council Rutherford Appleton Laboratory Proposals are being invited from the existing Europractice/Cadence user base of 378 European academic institutions These selected early adopters will then be able to more efficiently design 3D-IC systems for their research projects, e.g. in new computer architectures, with the possibility of fabrication via existing broker services offered by CMP (Circuits Multi-Project) in France Source John McLean Rutherford Appleton Laboratory

30 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy True 3D Mask Layout Editor MicroMagic MAX-3D Technology Files fully supported by Tezzaron

31 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy MicroMagic 3D viewer

32 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy MicroMagic 3D crossection

33 CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy Conclusion  A Design Platform resulted from the collaboration. CMC, CMP, MOSIS, FermiLab, Tezzaron, HEP Labs, NCSU  Industrial CAD vendors just starting addressing the features.  Still awaiting for new CAD tools dedicated to 3D-IC Integration : + 3D-IC Partitioning : both at the system level and the floor-planning level. + Standard 3D layout editor (i.e. Virtuoso 3D) + Sign-off tools for 3D-IC Integration : (3D-DRC, 3D-LVS, 3D-Extration)

Download ppt "CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy CAD Tools for 3D-IC and TSV-based designs Kholdoun TORKI"

Similar presentations

Tezzaron Semiconductor 06/14/2011 3D_IC for Real Chips Bob Patti, CTO 1.

Tezzaron Semiconductor 06/14/2011 3D_IC for Real Chips Bob Patti, CTO 1.
Ch.7 Layout Design Standard Cell Design TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology.

Ch.7 Layout Design Standard Cell Design TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology.
Dusan Petranovic & Karen Chow 3D-IC System Verification Methodology: Solutions and Challenges Marketing, Design to Silicon Division April 2011.

Dusan Petranovic & Karen Chow 3D-IC System Verification Methodology: Solutions and Challenges Marketing, Design to Silicon Division April 2011.
Ch.3 Overview of Standard Cell Design

Ch.3 Overview of Standard Cell Design
Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, and Sung Kyu Lim

Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, and Sung Kyu Lim
3D-MAPS: 3D Massively Parallel Processor with Stacked Memory Dae Hyun Kim, Krit Athikulwongse, Michael Healy, Mohammad Hossain, Moongon Jung, et al. Georgia.

3D-MAPS: 3D Massively Parallel Processor with Stacked Memory Dae Hyun Kim, Krit Athikulwongse, Michael Healy, Mohammad Hossain, Moongon Jung, et al. Georgia.
EECE579: Digital Design Flows

EECE579: Digital Design Flows
MICROELETTRONICA Design methodologies Lection 8. Design methodologies (general) Three domains –Behavior –Structural –physic Three levels inside –Architectural.

MICROELETTRONICA Design methodologies Lection 8. Design methodologies (general) Three domains –Behavior –Structural –physic Three levels inside –Architectural.
Spring 07, Jan 16 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Introduction Vishwani D. Agrawal James J. Danaher.

Spring 07, Jan 16 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Introduction Vishwani D. Agrawal James J. Danaher.
Design Team Project: Physical Design ( Layout ) Kyungseok Kim ELEC 7770 Advanced VLSI Design Lecturer: Dr. Vishwani D. Agrawal.

Design Team Project: Physical Design ( Layout ) Kyungseok Kim ELEC 7770 Advanced VLSI Design Lecturer: Dr. Vishwani D. Agrawal.
Split, 12 December 2005 University of Zagreb Slide 1 Chip level EMC measurements and simulations “Impact of Communications Technology to EMC“, COST 286.

Split, 12 December 2005 University of Zagreb Slide 1 Chip level EMC measurements and simulations “Impact of Communications Technology to EMC“, COST 286.
Interconnection and Packaging in IBM Blue Gene/L Yi Zhu Feb 12, 2007.

Interconnection and Packaging in IBM Blue Gene/L Yi Zhu Feb 12, 2007.
Design Tools, Flows and Library Aspects during the FE-I4 Implementation on Silicon Vladimir Zivkovic National Institute for Subatomic Physics Amsterdam,

Design Tools, Flows and Library Aspects during the FE-I4 Implementation on Silicon Vladimir Zivkovic National Institute for Subatomic Physics Amsterdam,
Hierarchical Physical Design Methodology for Multi-Million Gate Chips Session 11 Wei-Jin Dai.

Hierarchical Physical Design Methodology for Multi-Million Gate Chips Session 11 Wei-Jin Dai.
Robust Low Power VLSI R obust L ow P ower VLSI Memory Management Units for Instruction and Data Cache for OR1200 CPU Core Arijit Banerjee ASIC/SOC Class.

Robust Low Power VLSI R obust L ow P ower VLSI Memory Management Units for Instruction and Data Cache for OR1200 CPU Core Arijit Banerjee ASIC/SOC Class.
CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo 3D-IC prototyping service at CMP Kholdoun TORKI CMP 46,

CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo 3D-IC prototyping service at CMP Kholdoun TORKI CMP 46,
3D chip and sensor Status of the VICTOR chip and associated sensor Bonding and interconnect of chip and sensor Input on sensor design and interconnection.

3D chip and sensor Status of the VICTOR chip and associated sensor Bonding and interconnect of chip and sensor Input on sensor design and interconnection.
R. Kluit Electronics Department Nikhef, Amsterdam. Integrated Circuit Design.

R. Kluit Electronics Department Nikhef, Amsterdam. Integrated Circuit Design.
Global Timing Constraints FPGA Design Workshop. Objectives  Apply timing constraints to a simple synchronous design  Specify global timing constraints.

Global Timing Constraints FPGA Design Workshop. Objectives  Apply timing constraints to a simple synchronous design  Specify global timing constraints.
Application of through-silicon-via (TSV) technology to making of high-resolution CMOS image sensors Name: Qian YU Student ID: 20221416.

Application of through-silicon-via (TSV) technology to making of high-resolution CMOS image sensors Name: Qian YU Student ID:

Similar presentations

Ads by Google