1. 1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University pande@eecs.wsu.edu

2. 2 BOUNDARY SCAN

3. 3 Motivation for Standard n Bed-of-nails printed circuit board tester gone  We put components on both sides of PCB & replaced DIPs with flat packs to reduce inductance n Nails would hit components  Reduced spacing between PCB wires n Nails would short the wires  PCB Tester must be replaced with built-in test delivery system -- JTAG does that  Need standard System Test Port and Bus  Integrate components from different vendors n Test bus identical for various components n One chip has test hardware for other chips

4. 4 Bed-of-Nails Tester Concept

5. 5 Purpose of Standard n Lets test instructions and test data be serially fed into a component- under-test (CUT) n JTAG can operate at chip, PCB, & system levels n Allows control of tri-state signals during testing n Lets other chips collect responses from CUT n Lets system interconnect be tested separately from components n Lets components be tested separately from wires

6. 6 Boundary Scan (BS) IEEE 1149.1 Standard Developed for testing chips on a printed circuit board (PCB). A chip with BS can be accessed for test from the edge connector of PCB. BS hardware added to chip: –Test Access port (TAP) added Four test pins A test controller FSM –A scan flip-flop added to each I/O pin. Standard is also known as JTAG (Joint Test Action Group) standard.

7. 7 System Test Logic

8. 8 System Configuration Each pin of the chip has a register at that position Serial connection of this register – boundary register TDI – Serial input TDO – Serial output A number of registers can be connected between TDI and TDO

9. 9 Instruction Register Loading with JTAG

10. 10 System View of Interconnect

11. 11 Elementary Boundary Scan Cell

12. 12 Serial Board / MCM Scan

13. 13 Parallel Board / MCM Scan

14. 14 Independent Path Board / MCM Scan

15. 15 Tap Controller Signals n Test Access Port (TAP) includes these signals:  Test Clock Input (TCK) -- Clock for test logic n Can run at different rate from system clock  Test Mode Select (TMS) -- Switches system from functional to test mode  Test Data Input (TDI) -- Accepts serial test data and instructions -- used to shift in vectors or one of many test instructions  Test Data Output (TDO) -- Serially shifts out test results captured in boundary scan chain (or device ID or other internal registers)  Test Reset (TRST) -- Optional asynchronous TAP controller reset

16. 16 Tap Controller State Diagram

17. 17 Boundary SCAN Instructions

18. 18 SAMPLE / PRELOAD Instruction -- SAMPLE Purpose: 1. Get snapshot of normal chip input/output signals 2. Put data on bound. scan chain before next instr.

19. 19 SAMPLE/PRELOAD Pin inputs are passed to the system logic System logic outputs are also passed to the pin outputs Input and output pin values are captured in the first master-slave flip-flop controlled by the ClockDR signal The boundary scan ring prevents shifting of signals on the boundary scan chain, and the glitching they would cause, from being passed directly to the on-chip system logic This is accomplished by the second master-slave hold flip-flop, clocked by the UpdateDR signal

20. 20 SAMPLE / PRELOAD Instruction -- PRELOAD

21. 21 EXTEST Instruction n Purpose: Test off-chip circuits and board-level interconnections

22. 22 EXTEST Capture signals coming into the chip in the boundary scan register Drive the signals coming out of the chip from the boundary scan register The hold latches in the boundary scan register are held at their prior values

23. 23 Interconnect Test

24. 24 INTEST Instruction n Purpose: 1. Shifts external test patterns onto component 2. External tester shifts component responses out

25. 25 CLAMP Instruction n Purpose: Forces component output signals to be driven by boundary-scan register n Bypasses the boundary scan chain by using the one-bit Bypass Register n Optional instruction n May have to add RESET hardware to control on-chip logic so that it does not get damaged (by shorting 0’s and 1’s onto an internal bus, etc.)

26. 26 IDCODE Instruction n Purpose: Connects the component device identification register serially between TDI and TDO  In the Shift-DR TAP controller state n Allows board-level test controller or external tester to read out component ID n Required whenever a JEDEC identification register is included in the design

27. 27 Device ID Register --JEDEC Code 27 12 Part Number (16 bits) 11 1 Manufacturer Identity (11 bits) 0 ‘1’ (1 bit) 31 28 Version (4 bits) MSBLSB

28. 28 HIGHZ Instruction n Purpose: Puts all component output pin signals into high- impedance state n Control chip logic to avoid damage in this mode n May have to reset component after HIGHZ runs n Optional instruction

29. 29 BYPASS Instruction n Purpose: Bypasses scan chain with 1-bit register

30. 30 Optional / Required Instructions Instruction BYPASS CLAMP EXTEST HIGHZ IDCODE INTEST RUNBIST SAMPLE / PRELOAD USERCODE Status Mandatory Optional Mandatory Optional Mandatory Optional

31. 31 Single Boundary Scan Chain on a board

32. 32 Summary n Boundary Scan Standard has become absolutely essential --  No longer possible to test printed circuit boards with bed-of-nails tester  Not possible to test multi-chip modules at all without it  Now getting widespread usage